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參數(shù)資料
| 型號： | M25PE40VMP6TG |
| 廠商： | 意法半導體 |
| 元件分類： | DRAM |
| 英文描述： | 4 Mbit Uniform Sector, Serial Flash Memory |
| 中文描述： | 4兆位統(tǒng)一部門，串行閃存 |
| 文件頁數(shù)： | 10/60頁 |
| 文件大?。?/td> | 315K |
| 代理商： | M25PE40VMP6TG |
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SPI modes
M25PE40
10/60
3
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
CPOL=0, CPHA=0
CPOL=1, CPHA=1
●
●
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in
Figure 5
, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
●
●
Figure 4.
Bus master and memory devices on the SPI bus
1.
Figure 4
shows an example of three devices connected to an MCU, on an SPI bus. Only one
device is selected at a time, so only one device drives the Serial Data Output (Q) line at a
time, the other devices are high impedance. Resistors R (represented in
Figure 4
) ensure
that the is not selected if the Bus Master leaves the S line in the high impedance state. As
the Bus Master may enter a state where all inputs/outputs are in high impedance at the
same time (for example, when the Bus Master is reset), the clock line (C) must be connected
to an external pull-down resistor so that, when all inputs/outputs become high impedance,
the S line is pulled High while the C line is pulled Low (thus ensuring that S and C do not
become High at the same time, and so, that the t
SHCH
requirement is met). The typical value
of R is 100 k
, assuming that the time constant R*C
p
(C
p
= parasitic capacitance of the bus
line) is shorter than the time during which the Bus Master leaves the SPI bus in high
impedance.
The Write Protect or Top Sector Lock (W or TSL) signal should be driven, High or Low as appropriate.
AI13558
SPI Bus Master
SPI Memory
Device
SDO
SDI
SCK
C
Q
D
S
SPI Memory
Device
C
Q
D
S
SPI Memory
Device
C
Q
D
S
CS3
CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
W
or
TSL
HOLD
W
or
TSL
HOLD
W
or
TSL
HOLD
R
R
R
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
R
相關PDF資料 |
PDF描述 |
|---|---|
| M25PE40VMP6TP | 2A Standard Fixed Output LDO Regulators; Package: TO220FP-3; Constitution materials list: Packing style: Tube packaging; Package quantity: 50; Minimum package quantity: 500; |
| M25PE40VMW6G | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE40VMW6P | 2A Standard Fixed Output LDO Regulators with Shutdown Switch; Package: TO220FP-5; Constitution materials list: Packing style: Tube packaging; Package quantity: 50; Minimum package quantity: 500; |
| M25PE40VMW6TG | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE40VMW6TP | 2A Standard Fixed Output LDO Regulators; Package: TO220FP-3; Constitution materials list: Packing style: Tube packaging; Package quantity: 50; Minimum package quantity: 500; |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M25PE40-VMP6TG | 功能描述:閃存 SERIAL PAGE ERASE FLASH 4Mbit Datas RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M25PE40VMP6TP | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit, low voltage, Page-Erasable Serial Flash memory with byte alterability, 50 MHz SPI bus, standard pinout |
| M25PE40-VMP6TP | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:4 Mbit, page-erasable serial Flash memory with byte alterability, 75 MHz SPI bus, standard pinout |
| M25PE40VMW6G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit, low voltage, Page-Erasable Serial Flash memory with byte alterability, 50 MHz SPI bus, standard pinout |
| M25PE40-VMW6G | 功能描述:閃存 4 Mbit Lo Vltg Page Erasable Seral 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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