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參數(shù)資料
| 型號： | M25PE20-VMP6TP |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 4 Mbit Uniform Sector, Serial Flash Memory |
| 中文描述： | 4兆位統(tǒng)一部門，串行閃存 |
| 文件頁數(shù)： | 35/60頁 |
| 文件大?。?/td> | 310K |
| 代理商： | M25PE20-VMP6TP |
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M25PE20, M25PE10
Instructions
35/60
6.10
Page Program (PP)
The Page Program (PP) instruction allows Bytes to be programmed in the memory
(changing bits from 1 to 0, only). Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three address Bytes and at least one data Byte on Serial Data Input
(D). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data
exceeding the addressed page boundary roll over, and are programmed from the start
address of the same page (the one whose 8 least significant address bits (A7-A0) are all
zero). Chip Select (S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
Figure 17
.
If more than 256 Bytes are sent to the device, previously latched data are discarded and the
last 256 data Bytes are guaranteed to be programmed correctly within the same page. If
less than 256 Data Bytes are sent to device, they are correctly programmed at the
requested addresses without having any effects on the other Bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted Bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few Bytes (see
Table 22: AC
characteristics (50 MHz operation, T9HX (0.11μm) process)
).
Chip Select (S) must be driven High after the eighth bit of the last data Byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is t
PP
) is initiated. While the Page Program cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page that is Hardware Protected is not
executed.
Any Page Program (PP) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M25PE10-VMN6P | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE10-VMP6G | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE10-VMP6P | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE10-VMP6TG | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE10-VMP6TP | 4 Mbit Uniform Sector, Serial Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M25PE20-VMS6G | 制造商:Micron Technology Inc 功能描述: |
| M25PE20-VMW6G | 制造商:Micron Technology Inc 功能描述:SERIAL NOR - Trays |
| M25PE20-VMW6TG | 制造商:Micron Technology Inc 功能描述:SERIAL NOR - Tape and Reel |
| M25PE40 | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:4 Mbit, page-erasable serial Flash memory with byte alterability, 75 MHz SPI bus, standard pinout |
| M25PE40S-VMW6G | 制造商:Micron Technology Inc 功能描述:SERIAL NOR - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 4MBIT 75MHZ 8SO |
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