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參數(shù)資料
| 型號(hào)： | M24512-WBN5G |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 64K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁(yè)數(shù)： | 23/24頁(yè) |
| 文件大?。?/td> | 340K |
| 代理商： | M24512-WBN5G |
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M24512
8/24
Figure 6. Write Mode Sequences with WC=1 (data write inhibited)
Write Operations
Following a Start condition the bus master sends
The device acknowledges this, as shown in Figure
7, and waits for two address bytes. The device re-
sponds to each address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if Write
Control (WC) is driven High. Any Write instruction
with Write Control (WC) driven High (during a pe-
riod of time from the Start condition until the end of
the two address bytes) will not modify the memory
contents, and the accompanying data bytes are
not acknowledged, as shown in Figure 6.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 3) is sent first, followed by the Least Significant
Byte (Table 4). Bits b15 to b0 form the address of
the byte in memory.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10th bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
After the Stop condition, the delay tW, and the suc-
cessful completion of a Write operation, the de-
vice’s internal address counter is incremented
automatically, to point to the next byte address af-
ter the last one that was modified.
During the internal Write cycle, Serial Data (SDA)
is disabled internally, and the device does not re-
spond to any requests.
Byte Write
After the Device Select code and the address
bytes, the bus master sends one data byte. If the
addressed location is Write-protected, by Write
Control (WC) being driven High, the device replies
with NoAck, and the location is not modified. If, in-
stead, the addressed location is not Write-protect-
ed, the device replies with Ack. The bus master
terminates the transfer by generating a Stop con-
dition, as shown in Figure 7.
STOP
START
BYTE WRITE
DEV SEL
BYTE ADDR
DATA IN
WC
START
PAGE WRITE
DEV SEL
BYTE ADDR
DATA IN 1
WC
DATA IN 2
AI01120C
PAGE WRITE
(cont'd)
WC (cont'd)
STOP
DATA IN N
ACK
NO ACK
R/W
ACK
NO ACK
R/W
NO ACK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| M24512-WBN6 | 功能描述:電可擦除可編程只讀存儲(chǔ)器 5.5V 512K (64Kx8) RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| M24512-WBN6P | 制造商:STMicroelectronics 功能描述:EEPROM SERL-I2C 512KBIT 64KX8 3.3V/5V 8PDIP - Rail/Tube |
| M24512-WBN6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 Kbit Serial I睠 Bus EEPROM |
| M24512-WDW6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 Kbit Serial I睠 Bus EEPROM |
| M24512-WDW6G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 Kbit and 256 Kbit Serial I2C bus EEPROM with three Chip Enable lines |
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