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參數(shù)資料
| 型號： | M24128-MN6T |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 256/128 Kbit Serial IC Bus EEPROM Without Chip Enable Lines |
| 中文描述： | 一百二十八分之二百五十六千位串行IC總線的EEPROM芯片使能線無 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大小： | 135K |
| 代理商： | M24128-MN6T |
3/17
M24256, M24128
er clock, the master must have an open drain out-
put, and a pull-up resistor must be connected from
the SCL line to V
CC
. (Figure 3 indicates how the
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchro-
nization is not employed, and so the pull-up resis-
tor is not necessary, provided that the master has
a push-pull (rather than open drain) output.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to trans-
fer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to V
CC
. (Figure 3 indicates how the value of the
pull-up resistor can be calculated).
Write Control (WC)
The hardware Write Control pin (WC) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC=V
IL
) or disable (WC=V
IH
)
write instructions to the entire memory area. When
unconnected, the WC input is internally read as
V
IL
, and write operations are allowed.
When WC=1, Device Select and Address bytes
are acknowledged, Data bytes are not acknowl-
edged.
Please see the Application Note
AN404
for a more
detailed description of the Write Control feature.
DEVICE OPERATION
The memory device supports the I
2
C protocol.
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note
AN1001
. Any device that sends data on to the bus
is defined to be a transmitter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is known as the master,
and the other as the slave. A data transfer can only
be initiated by the master, which will also provide
the serial clock for synchronization. The memory
device is always a slave device in all communica-
tion.
Start Condition
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device con-
tinuously monitors (except during a programming
cycle) the SDA and SCL lines for a START condi-
tion, and will not respond unless one is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates communica-
tion between the memory device and the bus mas-
ter. A STOP condition at the end of a Read
command, after (and only after) a NoAck, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a suc-
cessful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
sending eight bits of data. During the 9
th
clock
pulse period, the receiver pulls the SDA bus low to
acknowledge the receipt of the eight data bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
Figure 3. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I
2
C Bus
AI01665
VCC
CBUS
SDA
RL
MASTER
RL
SCL
CBUS
100
0
4
8
12
16
20
CBUS (pF)
M
)
10
1000
fc = 400kHz
fc = 100kHz
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| M24128-WBN5T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256/128 Kbit Serial IC Bus EEPROM Without Chip Enable Lines |
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