- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358970 > M24128-BRBN6T (意法半導體) 256Kbit and 128Kbit Serial I2C Bus EEPROM With Three Chip Enable Lines PDF資料下載
參數(shù)資料
| 型號： | M24128-BRBN6T |
| 廠商： | 意法半導體 |
| 元件分類： | DRAM |
| 英文描述： | 256Kbit and 128Kbit Serial I2C Bus EEPROM With Three Chip Enable Lines |
| 中文描述： | 256Kbit和128Kbit的EEPROM串行I2C總線具有三個芯片使能線 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大小： | 135K |
| 代理商： | M24128-BRBN6T |
5/17
M24256, M24128
There are two modes both for read and write.
These are summarized in Table 4 and described
later. A communication between the master and
the slave is ended with a STOP condition.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 5) is sent first, followed by the Least significant
Byte (Table 6). Bits b15 to b0 form the address of
the byte in memory. Bit b15 is treated as a Don’t
Care bit on the M24256 memory. Bits b15 and b14
are treated as Don’t Care bits on the M24128
memory.
Table 4. Operating Modes
Note: 1. X =
V
IH
or V
IL
.
Mode
RW bit
WC
1
Data Bytes
Initial Sequence
Current Address Read
1
X
1
START, Device Select, RW
= ‘1’
Random Address Read
0
X
1
START, Device Select, RW = ‘0’, Address
1
X
reSTART, Device Select, RW = ‘1’
Sequential Read
1
X
≥
1
Similar to Current or Random Address Read
Byte Write
0
V
IL
1
START, Device Select, RW = ‘0’
Page Write
0
V
IL
≤
64
START, Device Select, RW
= ‘0’
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
S
S
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN
WC
S
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN 1
WC
DATA IN 2
AI01120C
PAGE WRITE
(cont'd)
WC (cont'd)
S
DATA IN N
ACK
ACK
ACK
NO ACK
R/W
ACK
ACK
ACK
NO ACK
R/W
NO ACK
NO ACK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M24128-B | 256/128 Kbit Serial I C Bus EEPROM With Three Chip Enable Lines |
| M24128 | 256/128 Kbit Serial IC Bus EEPROM Without Chip Enable Lines |
| M24128-BWMN6TG | 256Kbit and 128Kbit Serial I2C Bus EEPROM With Three Chip Enable Lines |
| M24128-BWMN6T | 256Kbit and 128Kbit Serial I2C Bus EEPROM With Three Chip Enable Lines |
| M24128-BWMN6P | 256Kbit and 128Kbit Serial I2C Bus EEPROM With Three Chip Enable Lines |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M24128-BRBN6TG | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Kbit, 64 Kbit and 32 Kbit serial IC bus EEPROM |
| M24128-BRBN6TP | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Kbit, 64 Kbit and 32 Kbit serial IC bus EEPROM |
| M24128-BRCS3G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Kbit, 64 Kbit and 32 Kbit serial IC bus EEPROM |
| M24128-BRCS3P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Kbit, 64 Kbit and 32 Kbit serial IC bus EEPROM |
| M24128-BRCS3TG | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Kbit, 64 Kbit and 32 Kbit serial IC bus EEPROM |
發(fā)布緊急采購，3分鐘左右您將得到回復。