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參數(shù)資料
| 型號： | M2004-31-622.0800LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 459K |
| 代理商： | M2004-31-622.0800LF |
M2004-x1 Datasheet Rev 1.1
4 of 12
Revised 16Jul2003
Integr ate d Circuit Systems , In c. ● Comm unication s Modules ● www.icst.com ● tel (508) 852-5400
M2004-X1
FREQUENCY TRANSLATION PLL SERIES
Preliminar y In f o r m atio n
FUNCTIONAL DESCRIPTION
The M2004-x1 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks
synchronized to one of two selectable input reference
clocks. An internal high “Q” SAW delay line provides a
low jitter clock signal.
The device can be pin-configured for feedback divider
and output divider values. These divider values can also
be set through serial programming. Output is LVPECL
compatible. External loop filter component values set
the PLL bandwidth to optimize jitter attenuation
characteristics.
The M2004-x1 is ideal for clock jitter attenuation and
frequency translation in 2.5 or 10 Gb optical network
line card applications.
Added Features and Device Variants
Hitless Switching with Phase Build-out (HS/PBO)
provides SONET/SDH MTIE and TDEV compliance
during a reference clock reselection when using the
internal mux (and also when using an external mux, in
two device variants).
A fixed Narrow Loop Bandwidth feature (Fixed NBW) is
also included in some of the device variants.
All of the variants of the device are defined as follows:
The M2004-01 is the base variant (it omits both
HS/PBO and Fixed NBW).
The M2004-11 includes HS/PBO triggered by either a
phase transient or internal mux reselection.
The M2004-21 includes HS/PBO triggered by
internal mux reselection only
and Fixed NBW.
The M2004-31 includes HS/PBO triggered by either
a phase transient or internal mux reselection
and
Fixed NBW.
The M2004-41 includes HS/PBO triggered by internal
mux reselection only.
The M2004-51 includes HS/PBO triggered by
internal mux reselection only
and Fixed NBW.
Input Reference Clocks
An internal input MUX is provided for input reference
clock selection. One input reference clock is selected
from between two single-ended LVCMOS / LVTTL clock
inputs. The maximum input frequency is 175MHz.
PLL Operation
The M2004-x1 is a complete clock PLL. It uses a phase
detector and configurable dividers to synchronize the
output of the VCSO with the selected reference clock.
The “M Divider” divides the VCSO output frequency,
feeding the result into the phase detector. The selected
input reference clock is fed into the other input of the
phase detector. The phase detector compares its two
inputs. It then causes the VCSO to increase or
decrease in speed as needed to phase- and frequency-
lock the VCSO to the reference input.
The value of M directly affects closed loop bandwidth.
The M Divider
The relationship between the VCSO center frequency
(Fvcso), the M divider, and the input reference
frequency (Fref_clk) is:
The product of M and the input frequency must be such
that it falls within the “l(fā)ock” range of the VCSO.
N Divider and Outputs
The M2004-x1 provides one differential LVPECL output
pair: FOUT, nFOUT. By using the N divider, the output
frequency can be the VCSO center frequency (Fvcso)
or 1/2, 1/4, or 1/8 Fvcso.
The N1 and N0 pins select the value for the N divider.
See Table 6, Pin Selection of N Divider Using N1:0
Pins, on pg. 3.
When the N divider is included, the complete relation-
ship for the output frequency (Fout) is defined as:
Configuration of M and N Dividers
The M and N dividers can be set by pin configuration or
serial programming. The divider configuration of the
M2004-x1 is reset when the input pin MR is set HIGH. MR
is set LOW for divider configuration to be operational.
See Table 9, Pin Configuration & Serial
Device Variants and Corresponding Functions
Variant
Hitless Switching /
Phase Build-out Triggered by
Fixed
NBW
Phase Transient Mux Reselection
M2004-01
no
M2004-11
Yes
no
M2004-21
no
Yes
M2004-31
Yes
M2004-41
no
Yes
no
M2004-51
no
Yes
Fvcso
Fref_clk
M
×
=
Fout
Fvcso
N
-------------------
=
Fref_clk
M
N
--------
×
=
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