參數(shù)資料
型號(hào)： M2004-31-622.0800LF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36
封裝： 9 X 9 MM, CERAMIC, LCC-36
文件頁(yè)數(shù)： 12/12頁(yè)
文件大?。?/td> 459K
代理商： M2004-31-622.0800LF
M2004-x1 Datasheet Rev 1.1
9 of 12
Revised 16Jul2003
M2004-X1
FREQUENCY TRANSLATION PLL SERIES
Preliminar y In f o r m atio n
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, V
CC = 3.3V +5%,TA = 0
oC to +70 oC (commercial), F
VCSO = FOUT = 622-675MHz, Outputs terminated with 50 to VCC - 2V
T
A = -40
oC to +85 oC (industrial)
Symbol Parameter
Min
Typ
Max
Unit Conditions
F
IN
Input Frequency
REF_CLK0, REF_CLK1
1
175
MHz
S_CLOCK
50
MHz
F
OUT
Output Frequency
FOUT, nFOUT
38
700
MHz
APR
VCSO Pull-Range
Commercial
±120
±200
ppm
Industrial
±50
±150
ppm
PLL Loop
Constants 1
Note 1: Parameters needed for PLL Simulator software; see Tables 10 and 11, External Loop Filter Component Values, on pg. 7.
K
VCO
VCO Gain
800
kHz/V
R
IN
Internal Loop Resistor
M2004-41
16
k
M2004-21, M2004-31, M2004-51
2016
k
BW
VCSO
VCSO Bandwidth
700
kHz
Phase Noise
and Jitter
Φn
Single Side Band
Phase Noise
@622.08MHz
1
kHz Offset
-72
dBc/Hz
10
kHz Offset
-94
dBc/Hz
100
kHz Offset
-123
dBc/Hz
J(t)
Jitter (rms)
12
kHz to 20MHz
0.5
ps
50
kHz to 80MHz
0.5
ps
odc
Output Duty Cycle 2
N = 2, 4, or 8
45
50
55
%
N = 1
40
50
60
%
t
R
Output Rise Time 2
for FOUT, nFOUT
F
OUT =155.52MHz N = 4 (N1:0 = 10)
350
450
550
ps
20
% to 80%
F
OUT =311.04MHz N = 2 (N1:0 = 01)
325
425
500
ps
F
OUT =622.08MHz N = 1 (N1:0 = 00)
200
275
350
ps
t
F
Output Fall Time 2
for FOUT, nFOUT
F
OUT =155.52MHz N = 4 (N1:0 = 10)
350
450
550
ps
20
% to 80%
F
OUT =311.04MHz N = 2 (N1:0 = 01)
325
425
500
ps
F
OUT =622.08MHz N = 1 (N1:0 = 00)
200
275
350
ps
t
SETUP
Setup Time 3
M5:0, N1:0 to nP_LOAD
5
ns
S_DATA to S_CLOCK
t
HOLD
Hold Time 3
M5:0, N1:0 to nP_LOAD
5
ns
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
t
IPW
Input Pulse Width 4
S_LOAD
10
ns
t
LOCK
PLL Lock Time
100
ms
MTIE
Mean Time Interval Error 5 M2004-21, M2004-31,
M2004-41, M2004-51
Note 5: Requires proper loop filter settings. Consult factory.
Compliant with GR-253-CORE
相關(guān)PDF資料
PDF描述
M2004-51I622.0800LF PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36
M2004-42-622.0800LF 2004 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36
M2004-32-622.0800 2004 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36
M2004-42I622.0800LF 2004 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36
M2004-42-622.0800 2004 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36
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