IGLOO Low Power Flash FPGAs
Revision 23
5-7
DC & Switching, cont’d. Table 2-49 Minimum and Maximum DC Input and Output Levels for LVCMOS
3.3 V Wide Range is new.
2-39
Revision 9 (Jul 2008)
Product Brief v1.1
DC and Switching
Characteristics
Advance v0.3
As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core
voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to
1.5 V.
N/A
Revision 8 (Jun 2008)
As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core
voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to
1.5 V.
N/A
DC and Switching
Characteristics
Advance v0.2
Tables have been updated to reflect default values in the software. The default I/O
capacitance is 5 pF. Tables have been updated to include the LVCMOS 1.2 V I/O
set.
DDR Tables have two additional data points added to reflect both edges for Input
DDR setup and hold time.
The power data table has been updated to match SmartPower data rather then
simulation values.
AGL015 global clock delays have been added.
N/A
VMV parameters in one row. The word "output" from the parameter description for
VCCI and VMV, and table note 3 was added.
references to tables notes 4, 6, 7, and 8. VMV was added to the VCCI parameter
row, and table note 9 was added.
Temperature1, the maximum operating junction temperature was changed from
110° to 100°.
table title was modified to remove "as measured on quiet I/Os." Table note 2 was
revised to remove "estimated SSO density over cycles." Table note 3 was revised
to remove "refers only to overshoot/undershoot limits for simultaneous switching
I/Os.
"
EQ 2 was updated. The temperature was changed to 100°C, and therefore the
end result changed.
include PDC6 and PDC7. VCCI and VJTAG were removed from the statement
Mode1 was updated to include VCCPLL. Note 4 was updated to include PDC6
and PDC7.
Revision / Version
Changes
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