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參數(shù)資料
| 型號(hào)： | M1A3P1000L-1PQG208I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA M1 1KB FLASH 1M 208PQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | ProASIC3L |
| RAM 位總計(jì)： | 147456 |
| 輸入/輸出數(shù)： | 154 |
| 門數(shù)： | 1000000 |
| 電源電壓： | 1.14V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
ARM CortexTM-M1
Prod uct Br ief
7
For example:
Bytes 0–3 hold the first stored word
Bytes 4–7 hold the second stored word
The processor accesses data and code words in little-
endian format. Little-endian is the default memory
format for ARM processors.
In little-endian format, the byte with the lowest address
in a word is the least significant byte of the word. The
byte with the highest address in a word is the most
significant. The byte at address 0 of the memory system
connects to data lines 7–0.
Exceptions
The processor and the Nested Vectored Interrupt
Controller (NVIC) prioritize and handle all exceptions. All
exceptions are handled in Handler mode. Processor state
is automatically stored to the stack on an exception, and
automatically restored from the stack at the end of the
exception handler Interrupt Service Routine (ISR). The
following
features
enable
efficient,
low-latency
exception handling:
Automatic
state
saving
and
restoring.
The
processor pushes state registers on the stack
before entering the ISR, and pops them after
exiting the ISR with no instruction overhead.
Automatic reading of the vector table entry that
contains the ISR address in code memory or data
SRAM
Closely-coupled interface between the processor
and the NVIC to enable early processing of
interrupts
and
processing
of
late-arriving
interrupts with higher priority
Fixed number of interrupt priorities, from 2 bits, 4
levels
Separate stacks for Handler and Thread modes if
OS extensions are implemented
ISR control transfer using the calling conventions
of the C/C++ standard Procedure Call Standard for
the ARM Architecture (PCSAA)
Priority masking to support critical regions
Exception Types
Various types of exceptions exist in the processor. A fault
is an exception that results from an error condition.
Faults can be reported synchronously or asynchronously
to the instruction that caused them. In general, faults are
reported synchronously. Faults caused by writes over the
bus are asynchronous faults. A synchronous fault is
always reported with the instruction that caused the
fault. An asynchronous fault does not guarantee how it
is reported with respect to the instruction that caused
the fault. See Table 3 for a list and description of the
exceptions supported by ARM Cortex-M1
.
Table 3
Exception Types
Position
Exception
Type
Priority
Description
Activated
–
Stack top is loaded from first entry of vector table on Reset.
–
1
Reset
–3 (highest)
Invoked on power-up and warm Reset. On first instruction,
drops to lowest priority. Thread mode.
Asynchronous
2
Non-maskable
–2
Cannot be marked, prevented by activation, by any other
exception. Cannot be preempted by any other exception
other than Reset.
Asynchronous
3
Hard fault
–1
All classes of fault
Synchronous or
asynchronous
4–10
–
Reserved
–
11
SVCall
Configurable
System service call with SVC instruction
Synchronous
12–13
–
Reserved
–
14
PendSV
Configurable
Pendable request for system service. This is only pended by
software.
Asynchronous
15
SysTick
Configurable
System tick timer has fired.
Asynchronous
16–48
External
interrupt
Configurable
Asserted from outside the processor, IRQ[2n-1:0], and fed
through the NVIC (prioritized).
Asynchronous
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