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參數(shù)資料
| 型號： | M14100-PQG208C |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 10000 GATES, 125 MHz, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 105K |
| 代理商： | M14100-PQG208C |
1-399
Actel Mask Programmed Gate Arrays
MPGA Architecture
The Actel MPGA is built using a “sea-of-gates” architecture. A
solid, regularly ordered array of transistors is overlaid with a
multilevel metal interconnect. Surrounding this logic core is
an array of programmable power and I/O pads. Separate grids
provide power and ground supplies for the core logic and I/O
cells.
The highly dense structure of Actel MPGAs provides for a
cost-effective
solution
while
maintaining
the
high
performance of each particular design. This architecture
reduces die size for low cost while minimizing gate length and
shortening routing paths for excellent system performance.
The robust power supply grids provide high I/O current drive
without sacrificing high noise immunity. Since Actel FPGAs
use a similar gate array architecture, design migration is a
straightforward, simple process. Because of the advanced
technology employed by the MPGA, the internal and external
performance of each design is virtually assured to be
preserved or improved after migration. To simplify migration
further, the I/O pads are carefully arranged to allow FPGA pin
assignments to be directly transferred to the full line of
MPGA packages. For more information about the ease of
design migration from Actel FPGAs to MPGAs, see the
application note “Designing for Migration to Actel MPGAs.”
Power Dissipation
The power dissipation for an Actel MPGA is composed of two
parts: static power and active power. The static power is a
product of the standby supply current (Icc) and the DC
supply voltage (Vcc). Specifications for Icc and Vcc are
located in the “Electrical Specifications” section of this data
sheet. The active power is a product of equivalent
capacitance, square of the DC supply voltage, and average
switching frequency of the circuit. It is expressed in the
formula
Power (
W) = C
EQ VCC
2 f
where
CEQ is the equivalent capacitance in picofarads (pF)
VCC is the DC supply voltage in volts (V)
f is the switching frequency in megahertz (MHz)
Upon receipt of the “Design Start Checklist” and associated
materials, Actel calculates the MPGA active power
dissipation for each design based on this formula. This
calculation is immediately relayed to you so that you can
update system power specifications accordingly. Typically,
power dissipation of an Actel design is significantly lower for
the MPGA version versus the FPGA version.
Timing Characteristics
The timing characteristics for Actel MPGA devices are
consistent across family and device types. Typical I/O buffer,
internal logic cell, and internal routing delays are common to
all MPGA devices. The advanced technology of the devices
ensures
converted
designs
meet
or
exceed
FPGA
performance. Refer to the MPGA Timing Model diagram and
Timing Characteristics chart for detailed timing and delay
estimates.
Timing Derating
Timing derating factors due to temperature, voltage, and
process variations are summarized in the following tables and
graphs. Use these derating factors to determine device
performance at any particular condition within the electrical
and environmental specifications.
MPGA devices are manufactured in a CMOS process.
Therefore,
device
performance
varies
according
to
temperature, voltage, and process variations. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case processing.
Maximum timing parameters reflect minimum operating
voltage, maximum operating temperature, and worst-case
processing.
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