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參數(shù)資料
| 型號： | M14100-PQG208C |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 10000 GATES, 125 MHz, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 20/20頁 |
| 文件大?。?/td> | 105K |
| 代理商： | M14100-PQG208C |
1-397
Actel Mask Programmed Gate Arrays
Pin Description
Package pin assignments for an FPGA design are directly
transferred to the equivalent MPGA package because all I/O
and power pins are located in identical positions. While the
conversion of package pin assignments is transparent in the
end product, there are two small functional differences to
note between the device types. First, dedicated FPGA global
and debugging pins are general purpose MPGA I/O pins. Also,
dedicated FPGA programming voltage pins are Vcc or ground
pins on an MPGA. Refer to Table 1 for a complete
cross-reference of pin descriptions between the FPGA and
MPGA.
Table 1 FPGA-to-MPGA Pin Cross-Reference
FPGA Pin Description
MPGA Pin Description
CLK
Clock (ACT 1 only)
TTL Clock input for ACT 1 global clock distribution net-
work. This pin can also be used as an I/O.
→
No Change
If desired, TTL Clock input signals may be moved to any
MPGA I/O location.
CLKA
Clock A (ACT 3, 3200DX, 1200XL, and ACT 2
only)
TTL Clock input for clock distribution networks. This pin
can also be used as an I/O.
→
No Change
If desired, TTL Clock input signals may be moved to any
MPGA I/O location.
CLKB
Clock B (ACT 3, 3200DX, 1200XL, and ACT 2
only)
TTL Clock input for clock distribution networks. This pin
can also be used as an I/O.
→
No Change
If desired, TTL Clock input signals may be moved to any
MPGA I/O location.
DCLK
Diagnostic Clock
TTL Clock input for diagnostic probe and device program-
ming. Function is controlled by the MODE pin.
→
I/O
This pin is used as an I/O only. It is not used for diagnos-
tic probe or device programming functions on an MPGA.
GND
Ground
LOW supply voltage.
→
Ground
LOW supply voltage.
HCLK
Dedicated (Hard-wired) Array Clock
(ACT 3 only)
TTL Clock input for ACT 3 sequential modules. This pin
can also be used as an I/O.
→
No Change
If desired, TTL Clock input signals may be moved to any
MPGA I/O location.
I/O
Input/Output
The I/O pin functions as an input, output, three-state, or
bidirectional buffer. Unused pins are automatically driven
LOW by the Designer software.
→
I/O
User-dened MPGA I/O pins function identically to their
FPGA counterparts. However, unused pins are NC (no
connection) pins.
IOCLK Dedicated (Hard-wired) I/O Clock
(ACT 3 only)
TTL Clock input for ACT 3 I/O modules. This pin can also
be used as an I/O.
→
No Change
If desired, TTL Clock input signals may be moved to any
MPGA I/O location.
IOPCL
Dedicated (Hard-wired) I/O Preset/Clear
(ACT 3 only)
TTL input for ACT 3 I/O preset or clear. This pin can also
be used as an I/O.
→
No Change
If desired, this input signal may be moved to any MPGA
I/O location.
MODE
Mode
The MODE pin controls the use of diagnostic pins (DCLK,
PRA, PRB, SDI). When the MODE pin is HIGH, the spe-
cial functions are active. When the MODE pin is LOW, the
pins function as I/Os.
→
TEST (No Connection)
This pin is reserved for parametric testing and should be
connected to ground (LOW supply voltage).
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