參數(shù)資料
型號(hào)： M13S64164A-5TG
廠商： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類： DRAM
英文描述： 1M x 16 Bit x 4 Banks Double Data Rate SDRAM
中文描述： 4M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝： 0.400 X 0.875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-66
文件頁(yè)數(shù)： 18/49頁(yè)
文件大小： 1526K
代理商： M13S64164A-5TG
ES MT
Preliminary
M13S64164A
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 0.3 18/49
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is
interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read
command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point
the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock.
<Burst Length = 4,
CAS
Latency = 3>
Read Interrupted by a Write & Burst Stop
To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus
by placing the DQ’s(Output drivers) in a high impedance state. To insure the DQ’s are tri-stated one cycle before the beginning the
write operation, Burt stop command must be applied at least RU(CL) clocks
［
RU mean round up to the nearest integer
］
before
the Write command.
<Burst Length = 4,
CAS
Latency = 3>
t
CCD
C A S L at e n c y= 3
0
1
2
3
4
5
6
7
8
CO M M AN D
DQS
DQ 's
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Dout A
0
READ B
Dout A
1
Dout B
2
Dout B
3
Dout B
0
Dout B
1
C L K
C L K
C A S L at e n c y= 3
0
1
2
3
4
5
6
7
8
CO MM AN D
DQS
DQ 's
READ
NOP
W RITE
NOP
NOP
NOP
NOP
NOP
Dout 0
Burst Stop
Din 0
Dout 1
Din 1 Din 2
Din 3
C L K
C L K
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M13S64164A-6TG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S64164A-6TIG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks Double Data Rate SDRAM
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