參數(shù)資料
型號(hào)： M13S128324A
廠商： Elite Semiconductor Memory Technology Inc.
英文描述： 1M x 32 Bit x 4 Banks Double Data Rate SDRAM
中文描述： 100萬(wàn)× 32位× 4個(gè)銀行雙倍數(shù)據(jù)速率SDRAM
文件頁(yè)數(shù)： 7/49頁(yè)
文件大?。?/td> 888K
代理商： M13S128324A
ES MT
AC Operating Test Conditions
Parameter
M13S128324A
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8 7/49
Value
Unit
Input reference voltage for clock (V
REF
)
0.5*V
DDQ
V
Input signal maximum peak swing
1.5
V
Input signal minimum slew rate
1.0
V/ns
Input levels (V
IH
/V
IL
)
V
REF
+0.35/V
REF
-0.35
V
Input timing measurement reference level
V
REF
V
Output timing reference level
V
TT
V
AC Timing Parameter & Specifications
(V
DD
= 2.375V~2.75V, V
DDQ
=2.375V~2.75V, T
A
=0° to 70° )(Note)
(V
DD
= 2.5V~2.7V, V
DDQ
=2.5V~2.7V, T
A
= 0° to 70° (for speed -3.6))
-3.6
-4
-5
-6
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min Max
CL2
7.5
12
7.5
12
7.5
12
7.5
12
CL2.5
6.0
12
6.0
12
6.0
12
6.0
12
CL3
5.0
12
5.0
12
5.0
12
6.0
12
Clock Period
CL4
t
CK
3.6
12
4.0
12
5.0
12
6.0
12
ns
Access time from CLK/CLK
t
AC
-0.6
+0.6
-0.7
+0.7
-0.7
+0.7
-0.7
+0.7
ns
CLK high-level width
t
CH
0.45
0.55
0.45
0.55
0.45
0.55
0.45 0.55
t
CK
CLK low-level width
t
CL
0.45
0.55
0.45
0.55
0.45
0.55
0.45 0.55
t
CK
Data strobe edge to clock edge
t
DQSCK
-0.6
+0.6
-0.7
+0.7
-0.7
+0.7
-0.7
+0.7
ns
Clock to first rising edge of DQS delay
t
DQSS
0.8
1.2
0.8
1.2
0.8
1.2
0.8
1.2
t
CK
Data-in and DM setup time (to DQS)
t
DS
0.4
-
0.45
-
0.45
-
0.45
-
ns
Data-in and DM hold time (to DQS)
t
DH
0.4
-
0.45
-
0.45
-
0.45
-
ns
DQ and DM input pulse width (for each input)
t
DIPW
1.75
-
1.75
-
1.75
-
1.75
-
ns
Input setup time (fast slew rate)
t
IS
0.9
-
0.9
-
1.0
-
1.0
-
ns
Input hold time (fast slew rate)
t
IH
0.9
-
0.9
-
1.0
-
1.0
-
ns
Control and Address input pulse width
t
IPW
2.2
-
2.2
-
2.2
-
2.2
-
ns
DQS input high pulse width
t
DQSH
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
DQS input low pulse width
t
DQSL
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
DQS falling edge to CLK rising-setup time
t
DSS
0.2
-
0.2
-
0.2
-
0.2
-
t
CK
DQS falling edge from CLK rising-hold time
t
DSH
0.2
-
0.2
-
0.2
-
0.2
-
t
CK
Data strobe edge to output data edge
t
DQSQ
-
0.4
-
0.4
-
0.45
-
0.45
ns
Data-out high-impedance window from
CLK/
CLK
t
HZ
-0.7
+0.7
-0.7
+0.7
-0.7
+0.7
-0.7
+0.7
ns
Data-out low-impedance window from
CLK/CLK
t
LZ
-0.7
+0.7
-0.7
+0.7
-0.7
+0.7
-0.7
+0.7
ns
* speed -4 (CL3) must set VDD/VDDQ = 2.7V
±
0.1V
相關(guān)PDF資料
PDF描述
M13S2561616A 4M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S2561616A-4TG 4M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S2561616A-5TG 4M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S2561616A-6TG 4M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S256328A 2M x 32 Bit x 4 Banks Double Data Rate SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M13S128324A_09 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
M13S128324A_1 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
M13S128324A-3.6BG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
M13S128324A-4BG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
M13S128324A-4LG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM
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