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參數(shù)資料
| 型號： | M13S128324A |
| 廠商： | Elite Semiconductor Memory Technology Inc. |
| 英文描述： | 1M x 32 Bit x 4 Banks Double Data Rate SDRAM |
| 中文描述： | 100萬× 32位× 4個銀行雙倍數(shù)據(jù)速率SDRAM |
| 文件頁數(shù)： | 5/49頁 |
| 文件大小： | 888K |
| 代理商： | M13S128324A |
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ES MT
M13S128324A
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8 5/49
Absolute Maximum Rating
Parameter
Symbol
Value
Unit
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-0.5 ~ 3.6
V
Voltage on V
DD
supply relative to V
SS
V
DD
, V
DDQ
-1.0 ~ 3.6
V
Voltage on V
DDQ
supply relative to V
SS
V
DDQ
-0.5 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
C
°
Power dissipation
P
D
2
W
Short circuit current
I
OS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to V
SS
= 0V, T
A
= 0 to 70° )
Min
Max
Parameter
Symbol
-3.6
-4/5/6
-3.6
-4/5/6
Unit
Note
Supply voltage
V
DD
2.5
2.375
2.7
2.625
V
I/O Supply voltage
V
DDQ
2.5
2.375
2.7
2.625
V
I/O Reference voltage
V
REF
0.49*V
DDQ
0.51*V
DDQ
V
1
I/O Termination voltage (system)
V
TT
V
REF
- 0.04
V
REF
+ 0.04
V
2
Input logic high voltage
V
IH
(DC)
V
REF
+ 0.15
V
DDQ
+ 0.3
V
Input logic low voltage
V
IL
(DC)
-0.3
V
REF
- 0.15
V
μ
A
Input leakage current
I
I
-5
5
3
Output leakage current
I
OZ
-5
5
μ
A
Output High Current (Normal strength driver)
(V
OUT
=V
DDQ
-0.373V, min V
REF
, min V
TT
)
I
OH
-16.8
mA
Output Low Current (Normal strength driver)
(V
OUT
= 0.373V)
I
OL
+16.8
mA
Output High Current (Weak strength driver)
(V
OUT
=V
DDQ
-0.763V, min V
REF
, min V
TT
)
I
OH
-9
mA
Output Low Current (Weak strength driver)
(V
OUT
= 0.763V)
I
OL
+9
mA
Notes 1. V
REF
is expected to be equal to 0.5* V
DDQ
of the transmitting device, and to track variations in the DC level of the
same. Peak-to-peak noise on V
REF
may not exceed 2% of the DC value.
2. V
TT
is not applied directly to the device. V
TT
is system supply for signal termination resistors, is expected to be set
equal to V
REF
, and must track variations in the DC level of V
REF
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M13S128324A_09 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM |
| M13S128324A_1 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM |
| M13S128324A-3.6BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM |
| M13S128324A-4BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM |
| M13S128324A-4LG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Double Data Rate SDRAM |
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