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參數(shù)資料
| 型號： | M12S64322A |
| 廠商： | Elite Semiconductor Memory Technology Inc. |
| 英文描述： | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| 中文描述： | 為512k × 32位× 4個銀行同步DRAM |
| 文件頁數(shù)： | 15/46頁 |
| 文件大?。?/td> | 746K |
| 代理商： | M12S64322A |
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ES MT
M12S64322A
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision
:
1.0
15/46
COMMANDS
Mode register set command
(CS ,RAS ,CAS ,
WE
= Low)
The DRAM has a mode register that defines how the device operates. In this
command, A0 through A10 and BA0~BA1 are the data input pins. After power on, the
mode register set command must be executed to initialize the device.
The mode register can be set only when all banks are in idle state.
During 2CLK following this command, the DRAM cannot accept any other
commands.
Activate command
(CS ,RAS = Low,CAS ,
WE
= High)
The DRAM has four banks, each with 2,048 rows.
This command activates the bank selected by BA1 and BA0 and a row address
selected by A0 through A10.
This command corresponds to a conventional DRAM’s RAS falling.
Precharge command
(CS ,RAS ,
WE
= Low,CAS = High )
This command begins precharge operation of the bank selected by BA1 and BA0.
When A10 is High, all banks are precharged, regardless of BA1 and BA0. When A10
is Low, only the bank selected by BA1 and BA0 is precharged.
After this command, the DRAM can’t accept the activate command to the
precharging bank during t
RP
(precharge to activate command period).
This command corresponds to a conventional DRAM’s RAS rising.
CLK
CLK
CKE
CKE
CS
CS
RAS
RAS
WE
WE
BA0, BA1
(Bank select)
A10
A10
Add
Add
CAS
CAS
H
H
Row
Row
Fig. 1 Mode register set
command
Fig. 2 Row address stroble and
bank active command
CLK
CKE
(Bank select)
A10
(Precharge select)
Add
H
Fig. 3 Precharge command
BA0, BA1
(Bank select)
CS
RAS
WE
CAS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M12S64322A-6BG | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12S64322A-6TG | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12S64322A-7BG | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12S64322A-7TG | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| M13S128168A | 2M x 16 Bit x 4 Banks Double Data Rate SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M12S64322A_09 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12S64322A-6BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12S64322A-6TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12S64322A-7BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12S64322A-7TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32 Bit x 4 Banks Synchronous DRAM |
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