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參數(shù)資料
| 型號： | M1025-1026 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low-Cost PC Hardware Monitor ASIC |
| 中文描述： | 低成本PC硬件監(jiān)視器的ASIC |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 164K |
| 代理商： | M1025-1026 |
REV. A
ADM1025/ADM1025A
–4–
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Description
1
2
3
4
SDA
SCL
GND
V
CC
Digital I/O. Serial bus bidirectional data. Open-drain output.
Digital Input. Serial bus clock.
System Ground.
Power. Can be powered by +3.3 V standby power if monitoring in low power states is required.
This pin also serves as the analog input to monitor V
CC
.
Digital Input. Core voltage ID readouts from the processor. This value is read into the VID0–VID3
Status Register. It has an on-chip 100 k
pull-up resistor (ADM1025 only).
Digital Input. Core voltage ID readouts from the processor. This value is read into the VID0–VID3
Status Register. It has an on-chip 100 k
pull-up resistor (ADM1025 only).
Digital Input. Core voltage ID readouts from the processor. This value is read into the VID0–VID3
Status Register. It has an on-chip 100 k
pull-up resistor (ADM1025 only).
Digital Input. Core voltage ID readouts from the processor. This value is read into the VID0–VID3
Status Register. It has an on-chip 100 k
pull-up resistor (ADM1025 only).
Analog/Digital Input. Connected to cathode of external temperature sensing diode. If held high at
power-up, initiates NAND tree test mode.
Analog Input. Connected to anode of external temperature sensing diode.
Programmable Analog/Digital Input. Defaults to 12 V
IN
analog input at power-up, but may be pro-
grammed as VID4 Core Voltage ID readout from the processor. This value is read into the VID4
Status Register. In analog 12 V
IN
mode it has an on-chip voltage attenuator. In VID4 mode it has an
on-chip 300 k
pull-up resistor.
Analog Input. Monitors 5 V supply.
Analog Input. Monitors 3.3 V supply.
Analog Input. Monitors 2.5 V supply.
Analog Input. Monitors processor core voltage (0 V to 3.0 V).
Programmable Digital I/O. The lowest order programmable bit of the SMBus Address, sampled on
SMB activity as a three-state input. Can also be configured to give a minimum 20 ms low reset
output pulse. Alternatively, can be programmed as an interrupt output for temperature/voltage
interrupts. Functions as the output of the NAND tree in NAND tree test mode.
5
VID0
6
VID1
7
VID2
8
VID3
9
D–/NTI
10
11
D+
12 V
IN
/VID4
12
13
14
15
16
5 V
IN
3.3 V
IN
2.5 V
IN
V
CCPIN
ADD/
RST
/
INT
/NTO
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
SDA
ADD/
RST
/
INT
/NTO
ADM1025/
ADM1025A
SCL
V
CCPIN
GND
2.5V
IN
V
CC
3.3V
IN
VID0
5V
IN
VID1
12V
IN
/VID4
VID2
D+
VID3
D
–
/NTI
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