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參數(shù)資料
| 型號： | M1025-1026 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low-Cost PC Hardware Monitor ASIC |
| 中文描述： | 低成本PC硬件監(jiān)視器的ASIC |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 164K |
| 代理商： | M1025-1026 |
REV. A
–2–
ADM1025/ADM1025A–SPECIFICATIONS
(T
A
= T
MIN
to T
MAX
, V
CC
= V
MIN
to V
MAX
, unless otherwise noted.)
P
arameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER SUPPLY
Supply Voltage, V
CC
Supply Current, I
CC
3.0
3.30
1.4
32
5.5
2.5
500
V
mA
μ
A
(Note 1)
Interface Inactive, ADC Active
Standby Mode (Note 2)
TEMPERATURE-TO-DIGITAL CONVERTER
Internal Sensor Accuracy
Resolution
External Diode Sensor Accuracy
±
3
°
C
°
C
°
C
°
C
°
C
μ
A
μ
A
1
±
5
±
3
60
°
C
≤
T
A
≤
100
°
C; V
CC
= 3.3 V
Resolution
Remote Sensor Source Current
1
180
11
High Level
Low Level
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENUATORS)
Total Unadjusted Error, TUE
Differential Nonlinearity, DNL
Power Supply Sensitivity
Conversion Time (Analog Input or Internal Temperature)
Conversion Time (External Temperature)
Input Resistance (2.5 V, 3.3 V, 5 V, 12 V, V
CCPIN
)
OPEN-DRAIN DIGITAL OUTPUT ADD/
RST
/
INT
/NTO
Output Low Voltage, V
OL
High Level Output Leakage Current, I
OH
RST
Pulsewidth
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, V
OL
High Level Output Leakage Current, I
OH
SERIAL BUS DIGITAL INPUTS (SCL, SDA)
Input High Voltage, V
IH
Input Low Voltage, V
IL
Hysteresis
DIGITAL INPUT LOGIC LEVELS
(ADD, VID0–VID4, NTI)
5
VID0–3 Input Resistance
VID4 Input Resistance
±
2
±
1
%
LSB
%/V
ms
ms
k
(Note 3)
±
1
11.6
34.8
140
(Note 4)
(Note 4)
100
250
0.4
1
45
V
μ
A
ms
I
OUT
= –6.0 mA; V
CC
= 3 V
V
OUT
= V
CC
; V
CC
= 3 V
0.1
20
0.4
1
V
μ
A
I
OUT
= –6.0 mA; V
CC
= 3 V
V
OUT
= V
CC
0.1
2.1
V
V
mV
0.8
500
100
300
100
k
k
k
V
V
ADM1025 Only
ADM1025 Only
ADM1025A
Input High Voltage, V
IH6
Input Low Voltage, V
IL6
DIGITAL INPUT LEAKAGE CURRENT
Input High Current, I
IH
Input Low Current, I
IL
Input Capacitance, C
IN
SERIAL BUS TIMING
Clock Frequency, f
SCLK
Glitch Immunity, t
SW
Bus Free Time, t
BUF
Start Setup Time, t
SU:STA
Start Hold Time, t
HD:STA
Stop Condition Setup Time t
SU:STO
SCL Low Time, t
LOW
SCL High Time, t
HIGH
SCL, SDA Rise Time, t
R
SCL, SDA Fall Time, t
F
Data Setup Time, t
SU:DAT
Data Hold Time, t
HD:DAT
NOTES
1
All voltages are measured with respect to GND, unless otherwise specified.
2
Typicals are at T
= 25
°
C and represent most likely parametric norm. Shutdown current typ is measured with V
= 3.3 V.
3
TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC, multiplexer and on-chip input attenuators, including an external series input
protection resistor value between zero and 1 k
.
4
Total monitoring cycle time is nominally 114.4 ms. Monitoring Cycle consists of 6 Voltage + 1 Internal Temperature + 1 External Temperature readings.
5
ADD is a three-state input that may be pulled high, low or left open-circuit.
6
Timing specifications are tested at logic levels of V
IL
= 0.8 V for a falling edge and V
IH
= 2.2 V for a rising edge.
Specifications subject to change without notice.
2.1
0.8
–1
μ
A
μ
A
pF
V
IN
= V
CC
V
IN
= 0
1
5
400
kHz
ns
μ
s
ns
ns
ns
μ
s
μ
s
ns
ns
ns
ns
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
50
1.3
600
600
600
1.3
0.6
300
300
100
300
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