參數(shù)資料
型號(hào): M-ORT82G51BM680-DB
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: FPGA
英文描述: FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝: PLASTIC, FBGA-680
文件頁數(shù): 61/94頁
文件大?。?/td> 2104K
代理商: M-ORT82G51BM680-DB
Lattice Semiconductor
ORCA ORT82G5 Data Sheet
64
HSI Electrical and Timing Characteristics
Table 28. Serial Input Timing and Levels (CML I/O)
Embedded Core Timing Characteristics
Table 29 summarizes the end-to-end latencies through the embedded core for the various modes. All latencies are
given in clock cycles for system clocks at half the REFCLK_[A:B] frequency. For a REFCLK_[A:B] of 156.25 MHz, a
system clock cycle is 6.4 ns.
Table 29. Signal Latencies, Embedded Core
Parameter
Min
Typ
Max
Unit
Rise Time
See Eye Diagram, Figure 31.
ps
Fall Time
See Eye Diagram, Figure 31.
ps
Differential Swing
200
mVp-p
Common-mode Level
0.5
VDD15
V
Internal Buffer Resistance (Each input to VDDIB)
40
50
60
PLL Lock Time
50
s
Operating Mode
Signal Latency (max.)
Transmit Path
5 clock cycles
Receive Path
Multi-Channel Alignment Bypassed
1
4.5 clock cycles
With Multi-Channel Alignment
1
13.5-22.5 clock cycles
1. With multi-channel alignment, the latency is largest when the skew between channels is at the maximum that can be correctly
compensated for (18 clock cycles). The latency specied in the table is for data from the channel received rst.
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