參數(shù)資料
型號(hào)： M-ORT82G51BM680-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝： PLASTIC, FBGA-680
文件頁(yè)數(shù)： 31/94頁(yè)
文件大小： 2104K
代理商： M-ORT82G51BM680-DB
Lattice Semiconductor
ORCA ORT82G5 Data Sheet
37
Figure 17. Mixed Rate Transmit Clocking for a Single Quad (Similar Connections Would Be Used for Quad B)
Receive Clock Source Selection and Recommended Clock Distribution
In the receive path, one clock per bank of 4 channels, called RCK78[A:B], is sent to the FPGA logic. The control
register bits RCKSEL[0:1][A:B] are used to select the clock source for these clocks. The selection of the source for
RCK78[A:B] is controlled by these bits as shown in Table 12.
Table 12. RCK78[A:B] Source Selection
In the receive channel alignment bypass mode the data and recovered clocks for the 8 channels (4 per SERDES
quad) are independent. The data for each channel are synchronized to the recovered clock from that channel.
Figure 18. - Receive Clocking for a Single Quad (Similar Connections Would Be Used for Quad B)
RCKSEL0
RCKSEL1
Clock Source
0
Channel A
1
0
Channel B
0
1
Channel C
1
Channel C
Common Logic, Quad A
Channel AA
Channel AB
Channel AD
Channel AC
REFCLK[P:N]_A
2
100 MHz
TCK78A
TSYS_CLK_AA
TSYS_CLK_AC
TSYS_CLK_AB
TSYS_CLK_AD
FPGA
Logic
Two Channels of
2.0 Gbits/s (Full-Rate)
Outgoing Serial Data
Channel AA Selected
as Clock Source
50 MHz
÷ 2
25 MHz
Two Channels of
1.0 Gbits/s (Half-Rate)
Outgoing Serial Data
Common Logic, Quad A
Channel AA
Channel AB
Channel AD
Channel AC
REFCLK[P:N]_A
2
156.25 MHz
RCK78A
RWCKAA
RWCKAC
RSYS_CLK_A1
TSYS_CLK_AD
FPGA
Logic
Four Channels of
3.125 Gbits/s
Incoming Serial Data
78.125 MHz
RWCKAB
RWCKAD
All Recovered
Clocks at
78.125 MHZ
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