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參數(shù)資料
| 型號： | M-986-1R2P |
| 廠商： | CLARE INC |
| 元件分類： | 信令電路 |
| 英文描述： | MFC Transceivers |
| 中文描述： | TELECOM, MF SIGNALING CIRCUIT, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大小： | 520K |
| 代理商： | M-986-1R2P |
Serial Port Timing
Parameter
Min
-
20
20
244
20
20
399
-
-
220
220
100
Nom
-
-
-
-
-
-
488.28
-
-
244.14
244.14
-
Max
70
-
-
-
-
-
4770
30
30
2500
2500
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
d
(CH-FR)
t
d
(DX1-CL)
t
d
(DX2-CL)
t
h
(DX)
t
su
(DR)
t
h
(DR)
t
c
(SCLK)
t
f
(SCLK)
t
r
(SCLK)
t
w
(SCLKL)
t
w
(SCLKH)
t
su
(FS)
Internal framing delay from SCLK rising edge
DX bit 1 valid before SCLK falling edge
DX bit 2 valid before SCLK falling edge
DX hold time after SCLK falling edge
DR setup time before SCLK falling edge
DR hold time after SCLK falling edge
Serial port clock cycle time
Serial port clock fall time
Serial port clock rise time
Serial port clock low-pulse duration*
Serial port clock high-pulse duration*
FSX/FSR setup time before SCLK falling edge
* The duty cycle of the serial port clock must be within 45% to 55%.
Supply voltage range, V
CC
Input voltage range
Output voltage range
Ambient air temperature range
Storage temperature range
-0.3 V to 7 V
-0.3 V to 15 V
-0.3 V to 15 V
0°C to 70°C
-45°C to 150°C
Signal Description (continued)
Signal
DIP
Pinout
PLCC
Pinout
I/O/Z
Description
FR
37
41
O
8 kHz internal serial-port framing output. If internal clocking is
selected, serial-port transmit and receive operations occur
simultaneously on an active (high) FR framing pulse.
FSR
39
43
I
8 kHz external serial-port receive-framing input. If external clocking
is selected, data is received via the receive pins (DR1 and DR0) on
the active (low) FSR input. The falling edge of FSR initiates the
receive process, and the rising edge causes the M-986 to process
the data.
8 kHz external serial-port transmit-framing input. If external clocking
is enabled, data is transmitted on the transmit pins (DX1, DX0) on
the active (low) input. The falling edge of FSX initiates the transmit
process,and the rising edge causes the M-986 to internally load data
for the next cycle.
2.048 MHz serial-port clock. Master clock for transmitting and
receiving serial-port data. Configured as an input in external clocking
mode or output in internal clocking mode. Reset (RS) forces SCLK
to the high-impedance state.
FSX
38
42
I
SCLK
34
38
I/O/Z
www.clare.com
6
M-986-2R2
Rev. 3
Absolute Maximum Ratings Over Specified
Temperature
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at these or
any other conditions beyond those indicated in the opera-
tional sections of this data sheet is not implied. Exposure of
the device to the absolute maximum ratings for an extend-
ed period may degrade the device and effect its reliability.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M-986-2A1PL | MF Transceiver |
| M-986-2A1 | MF Transceiver |
| M-986-2A1P | MF Transceiver |
| M-986-2R2 | MFC Transceivers |
| M-986-2R2P | MFC Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M-986-1R2PL | 制造商:CLARE 制造商全稱:Clare, Inc. 功能描述:MFC Transceivers |
| M9862 | 制造商:Tamura Corporation of America 功能描述: |
| M-986-2A1 | 制造商:CLARE 制造商全稱:Clare, Inc. 功能描述:MF Transceiver |
| M-986-2A1P | 功能描述:固態(tài)繼電器-PCB安裝 MF Transceiver, dual channel, 40xpin RoHS:否 制造商:Omron Electronics 控制電壓范圍: 負載電壓額定值:40 V 負載電流額定值:120 mA 觸點形式:1 Form A (SPST-NO) 輸出設(shè)備:MOSFET 封裝 / 箱體:USOP-4 安裝風格:SMD/SMT |
| M-986-2A1PL | 功能描述:固態(tài)繼電器-PCB安裝 MF Transceiver, dual channel, 44xpin RoHS:否 制造商:Omron Electronics 控制電壓范圍: 負載電壓額定值:40 V 負載電流額定值:120 mA 觸點形式:1 Form A (SPST-NO) 輸出設(shè)備:MOSFET 封裝 / 箱體:USOP-4 安裝風格:SMD/SMT |
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