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參數(shù)資料
| 型號(hào)： | LXT9761HC |
| 英文描述： | LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC |
| 中文描述： | 網(wǎng)絡(luò)收發(fā)器|六角| QFP封裝| 208PIN |塑料 |
| 文件頁(yè)數(shù)： | 33/68頁(yè) |
| 文件大?。?/td> | 1177K |
| 代理商： | LXT9761HC |
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Low-Power Octal PHY
—
LXT9784
Datasheet
33
2.3.2
100BASE-TX Transmitter
The transmit subsection of the LXT9784 PHY device accepts di-bit data on TXD
n_
[1:0] (RMII
interface) or serial stream data on TXD
n
(SMII interface) while TXEN
n
is asserted (High). The
data is assembled into nibbles and passed to the 4B/5B encoder as long as TXEN
n
is active.
The 4B/5B encoder compiles the data into 5-bit-wide parallel symbols. These symbols are
scrambled and serialized into a 125 Mbps bit stream, converted by the analog transmit driver into
an MLT-3 waveform format, and transmitted onto the unshielded twisted pair (UTP) or Type 1
shielded twisted pair (STP) wire.
2.3.2.1
100BASE-TX 4B/5B Encoder
The 4B/5B encoder complies with the IEEE 802.3u 100BASE-TX standard. Four bits at a time are
accepted and encoded according to the TX 4B/5B look-up table. The lookup table matches a 5-bit
code to each 4-bit code. Refer to Table 12.
2.3.2.2
100BASE-TX Scrambler and MLT-3 Encoder
Data is scrambled in 100BASE-TX to reduce electromagnetic emissions during long transmissions
of high-frequency data codes. The scrambler logic accepts 5 bits from the 4B/5B encoder block,
then presents scrambled data to the MLT-3 encoder. The LXT9784 PHYs implement the 11-bit
Stream Cipher scrambler as adopted by the ANSI XT3T9.5 committee for unshielded twisted-pair
operation. The cipher equation used is: X[n] = X[n-11] + X[n-9] (mod 2).
The encoder receives the scrambled NRZ data stream from the scrambler and encodes the stream
into MLT-3 for presentation to the driver. MLT3 is similar to NRZI coding, but three levels are
output instead of two. There are three output levels +, 0 and -. When an NRZ
“
0
”
arrives at the
input of the encoder, the last output level is maintained unchanged (either +, 0 or -) When an NRZ
“
1
”
arrives at the input of the encoder, the output steps to the next level. The order of steps is
“
-
,0,+,0,-,0...
”
See
Figure 8
.
Figure 7. SMII Received Serial Data Stream
SYNC
MCLK
Receive stream direction
RXD_n
CRS
RX_DV
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
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