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參數(shù)資料
| 型號： | LXT972A |
| 廠商： | Intel Corp. |
| 英文描述： | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| 中文描述： | 3.3雙速快速以太網(wǎng)收發(fā)器數(shù)據(jù)表 |
| 文件頁數(shù)： | 6/70頁 |
| 文件大小： | 833K |
| 代理商： | LXT972A |
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LXT972A
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3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
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Carrier Sense, Loopback, and Collision Conditions............................................28
4B/5B Coding......................................................................................................33
BSR Mode of Operation......................................................................................39
Supported JTAG Instructions..............................................................................39
Device ID Register..............................................................................................39
Magnetics Requirements ....................................................................................40
RJ-45 Pin Comparison of NIC and Switch Twisted-Pair Interfaces ....................40
Absolute Maximum Ratings ................................................................................44
Operating Conditions ..........................................................................................44
Digital I/O Characteristics 1.................................................................................45
Digital I/O Characteristics - MII Pins ...................................................................45
I/O Characteristics - REFCLK/XI and XO Pins....................................................45
I/O Characteristics - LED/CFG Pins....................................................................45
100BASE-TX Transceiver Characteristics ..........................................................46
10BASE-T Transceiver Characteristics...............................................................46
10BASE-T Link Integrity Timing Characteristics.................................................46
100BASE-TX Receive Timing Parameters - 4B Mode........................................47
100BASE-TX Transmit Timing Parameters - 4B Mode.......................................48
10BASE-T Receive Timing Parameters..............................................................49
10BASE-T Transmit Timing Parameters.............................................................50
10BASE-T Jabber and Unjabber Timing Parameters .........................................51
10BASE-T SQE Timing Parameters...................................................................51
Auto Negotiation and Fast Link Pulse Timing Parameters..................................52
MDIO Timing Parameters ...................................................................................53
Power-Up Timing Parameters............................................................................54
RESET Pulse Width and Recovery Timing Parameters ....................................54
Register Set ........................................................................................................55
Register Bit Map..................................................................................................56
Control Register (Address 0)...............................................................................58
MII Status Register #1 (Address 1).....................................................................58
PHY Identification Register 1 (Address 2)...........................................................59
PHY Identification Register 2 (Address 3)...........................................................60
Auto Negotiation Advertisement Register (Address 4)........................................61
Auto Negotiation Link Partner Base Page Ability Register (Address 5)..............62
Auto Negotiation Expansion (Address 6) ............................................................63
Auto Negotiation Next Page Transmit Register (Address 7)...............................63
Auto Negotiation Link Partner Next Page Receive Register (Address 8) ...........64
Configuration Register (Address 16, Hex 10) .....................................................64
Status Register #2 (Address 17).........................................................................65
Interrupt Enable Register (Address 18)...............................................................66
Interrupt Status Register (Address 19, Hex 13)..................................................66
LED Configuration Register (Address 20, Hex 14) .............................................68
Transmit Control Register #2 (Address 30).........................................................69
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT972ALC | 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972M | Single-Port 10/100 Mbps PHY Transceiver |
| LXT9763 | Fast Ethernet 10/100 Hex Transceiver with Full MII |
| LXT9763HC | LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC |
| LXT9784 | Transceiver Hardware Integrity Function Overview |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT972ALC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972LCHFB8 | 制造商:LEVEL_ONE 功能描述: |
| LXT972M | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| LXT973QC | 制造商:Intel 功能描述:LAN Transceiver, Dual, 100 Pin, Plastic, QFP |
| LXT974 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers |
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