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參數(shù)資料
| 型號(hào)： | LXT971ABC |
| 英文描述： | LAN TRANSCEIVER|SINGLE|CMOS|BGA|64PIN|PLASTIC |
| 中文描述： | 網(wǎng)絡(luò)收發(fā)器|單|的CMOS | BGA封裝| 64管腳|塑料 |
| 文件頁(yè)數(shù)： | 32/68頁(yè) |
| 文件大小： | 1177K |
| 代理商： | LXT971ABC |
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LXT9784
—
Low-Power Octal PHY
32
Datasheet
2.3.1.8
100BASE-TX Receive Error Detection and Reporting
In 100BASE-TX mode, the PHYs detect errors in the receive data in a number of ways. Any of the
following conditions is considered an error:
If the SSD ("JK") symbol is not fully detected after idle
If an invalid symbol is detected at the 4B/5B decoder
If IDLE is detected in the middle of a frame (before "TR" symbol pair are detected)
When any of the above error conditions occurs, the PHY immediately indicates a receive error for
reception. In RMII mode the PHY asserts RXER
n
, and in SMII mode the PHY asserts the RXD_0
status bit.
Figure 5. RMII Data Reception
Figure 6. False Carrier Detect
Table 12. SMII RXD_[7:0] Contents
CRS
RX_DV
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
X
O
receive error
status, from
previous frame
Speed
0 = 10Mbps
1=100Mbps
Duplex
0=down
1 = up
Link
0=down
1 = up
Jabber
0 =OK
1=error
Upper Nibble
0 = invalid
1 = valid
False Carrier
Detect
1
X
1
One Data Byte (two MII data nibbles)
CRSDV_n
MCLK
RXD1_n
Preamble
SFD
Data
∫∫
∫∫
RXD0_n
0
0
0
0
0
0
0
0
1
x
x
x
x
x
0
0
0
0
0
0
0
0
1
1
1
1
1
1
x
x
x
x
x
0
0
0
0
0
∫∫
∫∫
∫∫
∫∫
CRSDV_n
MCLK
RXD1_n
False Carrier detected
∫∫
∫∫
RXD0_n
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
∫∫
∫∫
∫∫
∫∫
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