參數(shù)資料
型號(hào)： LXT914QE
英文描述： LAN Transceiver
中文描述： 網(wǎng)絡(luò)收發(fā)器
文件頁(yè)數(shù)： 22/42頁(yè)
文件大?。?/td> 561K
代理商： LXT914QE
LXT914
—
Flexible Quad Ethernet Repeater
22
Datasheet
2.5.1.1
Programmable Internal Squelch Level
The 10BASE-T port receivers have two squelch levels: a normal level or default setting and a
reduced level squelch (-4.5 dB) selected when the ERSQx is set in the Setup register. When used
with Low noise media such as shielded twisted-pair cabling, the reduced squelch level allows
longer loop lengths in the network.
2.5.1.2
Polarity Detection and Correction
The LXT914 10BASE-T ports detect and correct for reversed polarity by monitoring link pulses
and end-of-frame sequences. A reversed polarity condition is declared when the port receives
sixteen or more incorrect link pulses consecutively, or four frames with reversed start-of-idle
sequence. In these cases the receiver reverses the polarity of the signal and thereby corrects for this
failure condition. If the port enters the link fail state and no valid data or link pulses are received
within 96 to 128 ms, the polarity is reset to the default non-flipped condition. (If Link Integrity
Testing is disabled, polarity detection is based only on received data.)
2.5.2
10BASE-T Transmission
Each LXT914 10BASE-T port receives NRZ data from the repeater core and passes it through a
Manchester encoder. The encoded data is then transmitted to the twisted-pair network (the DO
circuit). The advanced integrated pulse shaping and filtering network produces the pre-distorted
and pre-filtered output signal to meet the 10BASE-T jitter template. An internal continuous
resistor-capacitor filter is used to remove any high-frequency clocking noise from the pulse
shaping circuitry. Integrated filters simplify the design work required for FCC compliant EMI
performance. During idle periods, the LXT914 10BASE-T ports transmit link integrity test pulses
in accordance with the 802.3 10BASE-T standard.
Data packets transmitted by the LXT914 contain a minimum of 56 preamble bits before the start of
frame delimiter (SFD). In the Asynchronous mode, preamble regeneration takes place on the
transmit side. In the Synchronous mode, the preamble is regenerated on the receive side and
distributed via the IRB. If the total packet is less than 96 bits including the preamble, the LXT914
extends the packet length to 96 bits by appending a Jam signal (1010...) at the end.
2.5.3
10BASE-T Link Integrity Testing
The LXT914 fully supports the 10BASE-T Link Integrity test function. The link integrity test
determines the status of the receive side twisted-pair cable. Link integrity testing is enabled unless
disabled via the DISLIx bit in the Setup register. When enabled, the receiver recognizes link
integrity pulses transmitted in the absence of data traffic. With no data packets or link integrity
pulses within 100 (±50) ms, the port enters a link fail state and disables its transmitter. The port
remains in the link fail state until it detects three or more data packets or link integrity pulses.
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