參數(shù)資料
型號(hào)： LXT914PE
英文描述： LAN HUB CONTROLLER
中文描述： 局域網(wǎng)集線器控制器
文件頁(yè)數(shù)： 16/42頁(yè)
文件大?。?/td> 561K
代理商： LXT914PE
LXT914
—
Flexible Quad Ethernet Repeater
16
Datasheet
2.3
Internal Repeater Circuitry
The basic repeater circuitry is shared among all the ports within the LXT914. It consists of a global
repeater state machine, several timers and counters and the timing recovery circuit. The timing
recovery circuit includes a FIFO for re-timing and recovery of the clock which is used to clock the
receive data out onto the IRB.
The shared functional blocks of the LXT914 are controlled by the global state machine (
Figure 3
).
This diagram and all associated notations used are in strict accordance with section 9.6 of the IEEE
802.3 standard.
The LXT914 also implements the Partition State Diagram as defined by the IEEE 802.3 standard
and shown in
Figure 4
. The value of CCLimit as implemented in the LXT914 is 64.
The CCLimit value sets the number of consecutive collisions that must occur before the port is
subjected to automatic partitioning. Auto-partition/re-connection is also supported by the LXT914
with Tw5 conforming to the standard requirement of 450 to 560 bit times.
2.4
Initialization
The following description applies to the initial power-on reset and to any subsequent hardware
reset. When a reset occurs (RESET pin pulled High for > 1 ms), the device senses the levels at the
various control pins (see
Table 3
) to determine the correct operating modes for Management,
LEDs, and the AUI port functions.
2.4.1
Local Management Mode Initialization
An internal pull-up causes the LXT914 to default to the Local management mode unless the LOC/
EXT pin is tied Low. In the Local mode the serial port is a unidirectional interface used only to
download setup parameters from an external device.
In a Locally managed multiple-repeater (daisy chain) configuration, the first repeater in the chain
performs special functions. The First Position Select (FPS) pin is used to establish position (FPS
High = First, FPS Low = Not First). After establishing the Hardware mode, each LXT914 monitors
the FPS pin to determine its position.
If FPS is High (First Position), the repeater performs the following functions:
1. Outputs a 1 MHz Serial Clock (SCLK). SCLK is derived from the 20 MHz SYSCLK input in
ASYNC mode and from BCLKIO in SYNC mode; it is supplied to the SCLK inputs of all
other repeaters on the bus and to the EEPROM.
2. Asserts Chip Select (CS) High to enable the EEPROM.
3. Outputs a serial 9-bit request-to-send (RTS) strobe. The programmable device responds to the
RTS strobe with a serial data stream containing the setup parameters for all repeaters in the
chain.
4. Clocks the first 48 serial data input (SDI) bits from the EEPROM into its setup register. Refer
to
Table 9
and
Table 10
for Setup Register bit assignments.
5. Asserts Serial Enable Output (SENO) Low to enable the next repeater in line.
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