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參數(shù)資料
| 型號： | LXT332PE |
| 英文描述： | Line Interface |
| 中文描述： | 線路接口 |
| 文件頁數(shù)： | 27/32頁 |
| 文件大?。?/td> | 395K |
| 代理商： | LXT332PE |
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Dual T1/E1 Line Interface Unit
—
LXT331
Datasheet
27
Peak detector squelch level
-
226
-
mV
Data decision threshold
DSX-1
63
70
77
% peak
E1
43
50
57
% peak
Table 12. LXT331 Master Clock and Transmit Timing Characteristics
(See
Figure 14
)
Parameter
Sym
Min
Typ
1
Max
Unit
Master clock frequency
DSX-1
MCLK
-
1.544
-
MHz
E1
MCLK
-
2.048
-
MHz
Master clock tolerance
MCLKt
-
± 50
-
ppm
Master clock duty cycle
MCLKd
10
-
90
%
Transmit clock frequency
DSX-1
TCLK
-
1.544
-
MHz
E1
TCLK
-
2.048
-
MHz
Transmit clock tolerance
TCLKt
-
± 50
-
ppm
Transmit clock duty cycle
TCLKd
10
-
90
%
TPOS/TNEG to TCLK setup time
tSUT
25
-
-
ns
TCLK to TPOS/TNEG Hold time
tHT
25
-
-
ns
1. Typical figures are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
Figure 14. LXT331 Transmit Clock Timing
Table 13. LXT331 Receive Characteristics
(See
Figure 15
)
Parameter
Sym
Min
Typ
1
Max
Unit
Test Conditions
PMRK/NMRK pulse width
T1
tMPW
-
324
-
ns
E1
tMPW
-
244
-
ns
Receiver throughput delay
tRXD
-
65
-
ns
3.0 V pulse
1. Typical figures are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
Table 11. Analog Specifications
(Over Recommended Operating Range) (Continued)
Parameter
Min
Typ
1
Max
Unit
Test Conditions
1. Typical figures are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
2. Input signal at TCLK is jitter-free.
3. Not production tested, but guaranteed by design and other correlation methods.
t
SUT
t
HT
TCLK
TPOS
TNEG
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