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參數(shù)資料
| 型號： | LXT310PE |
| 英文描述： | PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|LDCC|28PIN|PLASTIC |
| 中文描述： | 的PCM收發(fā)器|單|的T 1（DS1的）|的CMOS | LDCC | 28腳|塑料 |
| 文件頁數(shù)： | 19/26頁 |
| 文件大?。?/td> | 402K |
| 代理商： | LXT310PE |
T1 CSU/ISDN PRI Transceiver
—
LXT310
Datasheet
19
selecting the 22.5 dB LBO, and the EGL pin is tied low, allowing for full receiver gain. The
TAOS, LLOOP and RLOOP diagnostic modes are individually controllable. The RCLK input to
the OR gate at RLOOP allows for clocking of the RLOOP pin, which enables network loopback
detection. The receive and transmit line interfaces are identical to the Host mode application
shown in
Figure 7
.
Figure 8. Typical LXT310 Hardware Mode Application
TCLK
TPOS
TNEG
RNEG
RPOS
RCLK
T1/ESF
FRAMER
See Note 1
MCLK
TCLK
TPOS
TNEG
MODE
RNEG
RPOS
RCLK
XTALIN
XTALOUT
JASEL
LOS
TTIP
TGND
TAOS
LLOOP
RLOOP
LBO1
LBO2
NLOOP
RGND
RV+
RRING
RTIP
LATN
EGL
TRING
TV+
LXT310
TRANSCEIVER
LXP600A
CLAD
FSI
CLKO
1.544
MHz
2.048 MHz
6.176
MHz
1.0
μ
F
V+
100
0.1
μ
F
1.544 MHz
T1 Line
Transmit
1:2
0V
12.5
12.5
68
μ
F
NOTE:
The LXT310 is
compatible with a wide
variety of framing/
signaling devices.
CLKI
From
CMOS
Control
Logic
T1 Line
Receive
1:1
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