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參數(shù)資料
| 型號： | LXT301Z |
| 廠商： | Digital Data Communications GmbH |
| 英文描述： | ADVANCED T1/E1 SHORT-HAUL TRANSCEIVERS |
| 中文描述： | 先進(jìn)的T1/E1短途收發(fā)器 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 508K |
| 代理商： | LXT301Z |
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eé
L1
ê
INT
'2
,QWHUUXSW
+RVW 0RGH
This
LXT300Z Host
Mode
output goes Low to flag the host
processor when LOS or DPM go active. INT is an open-drain output and should be tied
to power supply RV+ through a resistor. INT is reset by clearing the respective register
bit (LOS and/or DPM).
(&ì
',
(TXDOL]HU &RQWURO ì
+: 0RGH
The signal applied at this pin in the
LXT300Z Hard-
ware Mode and LXT301Z
is used in conjunction with EC2 and EC3 inputs to determine
shape and amplitude of AMI output transmit pulses.
é
6',
',
6HULDO 'DWD ,Q
+RVW 0RGH
The serial data input stream is applied to this pin when the
LXT300Z
operates in the
Host Mode.
SDI is sampled on the rising edge of SCLK.
(&
',
(TXDOL]HU &RQWURO
+: 0RGH
The signal applied at this pin in the
LXT300Z Hard-
ware Mode and LXT301Z
is used in conjunction with EC1 and EC3 inputs to determine
shape and amplitude of AMI output transmit pulses.
è
6'2
'2
6HULDO 'DWD 2XW
+RVW 0RGH
The serial data from the on-chip register is output on
this pin in the
LXT300Z Host Mode.
If CLKE is High, SDO is valid on the rising edge
of SCLK. If CLKE is Low SDO is valid on the falling edge of SCLK. This pin goes to
a high-impedance state when the serial port is being written to and when CS is High.
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',
(TXDOL]HU &RQWURO ê
+: 0RGH
The signal applied at this pin in the
LXT300Z Hard-
ware Mode and LXT301Z
is used in conjunction with EC1 and EC2 inputs to determine
shape and amplitude of AMI output transmit pulses.
CS
',
&KLS 6HOHFW
+RVW 0RGH
This input is used to access the serial interface in the
LXT300Z Host Mode.
For each read or write operation, CS must transition from High
to Low, and remain Low.
5/223
',
5HPRWH /RRSEDFN
+: 0RGH
This input controls loopback functions in the
LXT300Z Hardware Mode and LXT301Z
. Setting RLOOP High enables the Remote
Loopback mode. Setting both RLOOP and LLOOP High causes a Reset.
6&/.
',
6HULDO &ORFN
+RVW 0RGH
This clock is used in the
LXT300Z Host Mode
to write data
to or read data from the serial interface registers.
//223
',
/RFDO /RRSEDFN
+: 0RGH
This input controls loopback functions in the
LXT300Z
Hardware Mode and LXT301Z
. Setting LLOOP High enables the Local Loopback
&/.(
',
&ORFN (GJH
+RVW 0RGH
Setting CLKE High causes RPOS and RNEG to be valid on
the falling edge of RCLK, and SDO to be valid on the rising edge of SCLK. When
CLKE is Low, RPOS and RNEG are valid on the rising edge of RCLK, and SDO is
valid on the falling edge of SCLK.
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',
7UDQVPLW $OO 2QHV
+: 0RGH
When High, TAOS causes the
LXT300Z (Hardware
Mode) and LXT301Z
to transmit a continuous stream of marks at the TCLK frequency.
Activating TAOS causes TPOS and TNEG inputs to be ignored. TAOS is inhibited dur-
ing Remote Loopback.
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