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參數(shù)資料
| 型號： | LXT301Z |
| 廠商： | Digital Data Communications GmbH |
| 英文描述： | ADVANCED T1/E1 SHORT-HAUL TRANSCEIVERS |
| 中文描述： | 先進的T1/E1短途收發(fā)器 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 508K |
| 代理商： | LXT301Z |
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Received data outputs. A signal on
RNEG corresponds to receipt of a negative pulse on RTIP and RRING. A signal on
RPOS corresponds to receipt of a positive pulse on RTIP and RRING. RNEG and
RPOS outputs are Non-Return-to-Zero (NRZ). Both outputs are stable and valid on the
rising edge of RCLK.
LXT300Z only: In the Host Mode, CLKE determines the clock edge at which these out-
puts are stable and valid. In the Hardware Mode both outputs are stable and valid on
the rising edge of RCLK.
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This is the clock recovered from the signal received at RTIP and
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An external crystal operating at four
times the bit rate (6.176 MHz for DSX-1, 8.192 MHz for E1 applications with an 18.7
pF load) is required to enable the jitter attenuation function of the LXT300Z. These
pins may also be used to disable the jitter attenuator by connecting the XTALIN pin to
the positive supply through a resistor, and floating the XTALOUT pin.
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DPM goes High when the transmit monitor loop
(MTIP and MRING) does not detect a signal for 63 ±2 clock periods. DPM remains
High until a signal is detected.
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LOS goes High when 175 consecutive spaces have been detected.
LOS returns Low when a mark is detected.
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Differential Driver Outputs. These outputs are
designed to drive a 25
load. The transmitter will drive 100
shielded twisted-pair
cable through a 1:2 step-up transformer without additional components. To drive
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coaxial cable, two 2.2
resistors are required in series with the transformer.
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The AMI signal received from the line is applied at these
pins. A center-tapped, center-grounded, 2:1 step-up transformer is required on these
pins. Data and clock from the signal applied at these pins are recovered and output on
the RPOS/RNEG and RCLK pins.
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