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參數(shù)資料
| 型號： | LXP730 |
| 廠商： | Intel Corp. |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 6/70頁 |
| 文件大?。?/td> | 531K |
| 代理商： | LXP730 |
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LXP730
—
Multi-Rate DSL Framer
6
Datasheet
Tables
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LXP730 Pin Descriptions ....................................................................................11
Common Transport & Line Rates........................................................................19
Kloop Values.......................................................................................................20
Typical ADPLL Register Settings, MCLK = 16.384MHz......................................22
Pin settings for HWC DSL Line Rates.................................................................23
MDSL Frame Sync Word (FSW) Patterns ..........................................................25
MDSL Frame Format ..........................................................................................25
Absolute Maximum Ratings ................................................................................33
Recommended Operating Conditions.................................................................33
I/O Electrical Characteristics...............................................................................33
Generic PCM Bus Interface Timing Specifications (See
Figure 11
)....................34
Codec Interface Timing Specifications (See
Figure 14
)......................................37
Asynchronous Port Timing Specifications (See
Figure 15
).................................38
OSIO Timing Specifications (See
Figure 16
) ......................................................39
MDSL Interface Input Timing Specifications (See
Figure 17
) .............................40
MDSL Interface Output Timing Specifications (See
Figure 18
) ..........................40
E1/T1 Input Timing Specifications (See
Figure 19
).............................................41
E1/T1 Output Timing Specifications (See
Figure 20
)..........................................42
Microprocessor Write Cycle Specifications
—
Motorola Mode (See
Figure 21
)....42
Microprocessor Read Cycle Specifications - Motorola Mode (See
Figure 22
)....43
Microprocessor Write Cycle Specifications
—
Intel Mode (See
Figure 23
)...........44
Microprocessor Read Cycle Specifications
—
Intel Mode (See
Figure 24
) ..........45
MCLK Frequency and Tolerance Specification...................................................45
Reset Timing Specifications (See
Figure 25
)......................................................46
LXP730 Register Summary.................................................................................47
Number MDSL Channels....................................................................................49
Timeslot to Channel 1 .........................................................................................49
Timeslot to Channel 2 .........................................................................................49
Timeslot to Channel 3 .........................................................................................50
Timeslot to Channel 4 .........................................................................................50
Timeslot to Channel 5 .........................................................................................50
Timeslot to Channel 6 .........................................................................................51
Timeslot to Channel 7 .........................................................................................51
Timeslot to Channel 8 .........................................................................................51
Timeslot to Channel 9 .........................................................................................52
Timeslot to Channel 10.......................................................................................52
Timeslot to Channel 11.......................................................................................52
Timeslot to Channel 12.......................................................................................53
Timeslot to Channel 13.......................................................................................53
Timeslot to Channel 14.......................................................................................53
Timeslot to Channel 15.......................................................................................54
Timeslot to Channel 16.......................................................................................54
Timeslot to Channel 17.......................................................................................54
Timeslot to Channel 18.......................................................................................55
Reserved Registers.............................................................................................55
Wander Reduction Register................................................................................55
FIFO/Miscellaneous Control Register .................................................................56
Slip Buffer Lower Threshold................................................................................56
Slip Buffer Upper Threshold................................................................................57
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