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參數(shù)資料
| 型號： | LX1692IDW-TR |
| 廠商： | MICROSEMI CORP-ANALOG MIXED SIGNAL GROUP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.1 A SWITCHING CONTROLLER, PDSO20 |
| 封裝： | ROHS COMPLIANT, PLASTIC, SOIC-20 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 271K |
| 代理商： | LX1692IDW-TR |
LX1692
PRODUCTION DATA SHEET
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 3
Copyright
2004
Rev. 1.1, 2/9/2006
WWW
.Microse
m
i
.CO
M
Full Bridge Resonant CCFL Controller
TM
FUNCTIONAL PIN DESCRI PTION (CONTINUED)
Name
Description
C_BST
Burst dimming mode frequency set capacitor. Internal bias currents set via the I_R pin are scaled down and
used to charge and discharge the capacitor connected at the C_BST pin. The voltage at the C_BST pin is a
sawtooth waveform displaying a voltage that ranges from 0.5V to 2.5V. The frequency of the PWM for digital
dimming is set by the I_R and C_BST pins.
R
_
I
BST
_
C
DIM
R
.
C
98039
F
=
where RI_R is in
Ω
K
and CC_BST is in nF, FDIM is Hz
The internal burst oscillator frequency can also be forced to follow an external clock signal at this pin. In this
case, the programmed frequency must be lower than the external frequency.
C_TO
Time Out set capacitor. An external capacitor is charged with an on chip current source to create a voltage
ramp. Over voltage fault shutdown is disabled until C_TO voltage rises above 3.5V, providing a user
programmed strike interval. After C_TO is reached to the internal threshold level, then it will be discharged to
0V. Also Short lamp detection will be disabled until C_TO voltage rises above 0.5V. Strike Interval time is
TO
_
C
R
_
I
C
R
035
.
0
t
=
where RI_R is in
Ω
K
and CC_TO is in F
And Short lamp detection disable time internal is
TO
_
C
R
_
I
C
R
005
.
0
t
=
VDDA
Analog Voltage Regulator Output. This output pin is used to connect an external capacitor to stabilize and filter
the on-chip LDO regulator. The input of the LDO is the switched VDDP supply. The LDO output is nominally
4.0V and is used to drive all circuitry except the output buffers at AOUT, BOUT, COUT and DOUT. The drop
out voltage is typically 0.05V at 2mA; the average internal load. This output can supply up to a 5mA external
load. The output capacitor should be a 100nF ceramic dielectric type.
ENABLE
Chip Enable Input. If logic high, all functions are enabled. If logic low, internal power is disconnected from the
VDDP pin, disabling all functions. Logic threshold is 1.85V / 1.35V maximum over supply and temperature
range. Maximum current into VDDP when ENABLE < 0.8V, is 50A. ENABLE may be connected directly to
VDDP if the disable function is not used
BRITE_D
Brightness Control Input for digital dimming. The input signal can be a DC voltage or low frequency PWM
signal. Active DC voltage range is 0.5V to 2.5V. Signals above 2.5V makes continuous operation, voltages
between 0.5V and 2.5V makes PWM digital dimming. Digital dimming pulse width varies from 100% duty at
2.5V to 0% duty at 0.5V. A minimum BRITE_D input voltage (externally supplied) of approximately TBDV is
required to prevent fault stop. PWM inputs from either 3.3V or 5V logic are permissible. Frequency may range
up to 1KHz. Max jitter of more than 1s / V on this input may cause noticeable lamp flicker. Refer to Dimming
configuration Table for setting.
ICOMP
Error Amp Output for the lamp current regulator. This error amplifier is a gm type and does not require an
external capacitor for stability. An External capacitor is connected from this pin to Ground to adjust loop
response of the inverter module. This capacitor value can vary from 0.1nF to 33nF as required by specific
applications. Error amplifier output voltage is not allowed to exceed the peak voltage of its associated
comparator ramp by more than 10%.
VCOMP
Voltage loop compensation pin for transformer output voltage regulation. An external capacitor is connected
from this pin to Ground to adjust loop response. An external resistor divider is connected to limit the maximum
output duty cycle while the IC is operating in strike mode. Recommended resistor divider value are 100K from
VDDA and 300K to GND.
BRITE_A
Brightness control input for analog dimming. The input signal can be a DC voltage or a PWM signal that has
been externally filtered to DC. Active DC voltage range is 0 to 2V. Signals above 2V and below 0.45V are
clamped and do not change amplitude of output current.
VIN_SNS
Input voltage sense pin. An external resistor and capacitor are connected to this pin to control slope of the
frequency tracking oscillator and open lamp voltage regulator timing ramp. Ramp slope becomes steeper as the
external bridge power supply increases providing rapid line voltage transient response.
This feature permits using very low profile transformers that can easily saturate if simultaneously exposed to
both high voltage and high duty cycle operation.
PP
AA
CC
KK
AA
GG
EE
DD
AA
TT
AA
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