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參數(shù)資料
| 型號(hào)： | LX1692IDW-TR |
| 廠商： | MICROSEMI CORP-ANALOG MIXED SIGNAL GROUP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.1 A SWITCHING CONTROLLER, PDSO20 |
| 封裝： | ROHS COMPLIANT, PLASTIC, SOIC-20 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 271K |
| 代理商： | LX1692IDW-TR |
LX1692
PRODUCTION DATA SHEET
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 4
Copyright
2004
Rev. 1.1, 2/9/2006
WWW
.Microse
m
i
.CO
M
Full Bridge Resonant CCFL Controller
TM
FUNCTIONAL PIN DESCRI PTION (CONTINUED)
Name
Description
OC_SNS
Over current sense input. The OC_SNS input is compared to a 2V reference. The comparator output shuts off
the PWM outputs to prevent possible secondary failures. The input voltage at this pin is not rectified. Normal
operating voltage levels will be in the range of ±0.5V to VDDP. An abnormal voltage can operate continuously
as high as ±7V peak under load fault conditions. Transients under fault conditions up to ±11 VPEAK are
permitted. An input voltage above 4 peak but less than ±11V peak may cause saturation but will not cause
malfunction, phase reversal, or reliability issues with the IC.
OV_SNS
Over Voltage Sense Input. This input pin monitors a voltage divider (approximately 1000:1) placed across the
lamp. During strike mode the frequency tracking oscillator uses the voltage waveform from the divider to
determine and track load resonant frequency, and the open lamp voltage regulator uses it to regulate open
circuit voltage. During both run and strike modes, fault detection comparators monitor voltage amplitude to
determine if load opens or shorts occur. See functional description section for details on internal circuit
operation. Frequency range of the input signal is from 30KHz to 150KHz and must not be rectified. Normal
operating voltage levels will be in the range of ±0.5 to ±VDDP peak, centered about +0.2 VDC. An abnormal
voltage can operate continuously as high as ±7V peak under load fault conditions. Transients under load fault
conditions up to ±11V peak are permitted. An input voltage above ±4Vpk may cause saturation, but will not
cause malfunction, phase reversal, or reliability issues with the IC
ISNS
Current Sense Input. The ISNS input is full wave rectified by an On-Chip circuit, then presented to the inverting
input of the current error amplifier. Frequency range of the input signal is DC to 200KHz. The ISNS pin also
monitors lamp current to determine if the lamp is ignited. If a single cycle at the ISNS pin is greater than 0.7V,
the strike / run flip flop is clocked to the RUN state and threshold of the strike comparator is lowered to 0.3V.
During RUN mode current levels are continuously monitored to detect less than 0.3V. A counter clocked by
RMPD_OUT is reset each time current is sensed at this input. If the counter overflows (256 counts) a fault latch
is set which shuts down the IC. This fault is expected to occur when the lamp is shorted to ground through an
impedance of less than 2K ohms or the ISNS resistor itself is shorted. The counter is inhibited during digital
dimming off time. Normal operating voltage levels will be in the range of ±0.5V to ±5.5V. An abnormal voltage
can operate continuously as high as ±7V peak under load fault conditions. Transients under fault conditions up
to ±11 VPK are permitted. Input voltages up 4V peak are linearly rectified. An input voltage above ±4V peak
but less than ±11V peak may cause saturation but will not cause malfunction, phase reversal, or reliability
issues with the IC.
DOUT
A buffer P-FET driver output. Has a 20K pull up, RDSON nominal =
Ω
30
COUT
A buffer P-FET driver output. Has a 20K pull up, RDSON nominal =
Ω
30
BOUT
A buffer N-FET driver output. Has a 20K pull down, RDSON nominal =
Ω
30
AOUT
A buffer N-FET driver output. Has a 20K pull down, RDSON nominal =
Ω
30
GND
Ground
VDDP
Input Supply Voltage, 4.5V to 5.5V input range. VDDP is switched (see ENABLE) to remove power from chip.
An LDO regulator follows the switch and generates 4.0VDC. The output driver stages are powered directly from
the VDDP input. The output capacitor should be a 1000nF or larger ceramic dielectric type.
PP
AA
CC
KK
AA
GG
EE
DD
AA
TT
AA
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