參數(shù)資料
型號： LV8112V
元件分類： 運動控制電子
英文描述： BRUSHLESS DC MOTOR CONTROLLER, 3 A, PDSO44
封裝： 0.275 INCH, SSOP-44
文件頁數(shù)： 7/13頁
文件大?。?/td> 299K
代理商： LV8112V
LV8112V
No.A1645-3/13
Continued from preceding page.
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
FG Output
Output ON resistance
VOL(FG)
IFG = 7mA
20
30
Ω
Output leakage current
IL(FG)
VO = 5V
10
μA
PWM Oscillator
High level output voltage
VOH(PWM)
2.95
3.2
3.45
V
Low level output voltage
VOL(PWM)
1.3
1.5
1.7
V
External capacitor charge current
ICHG(PWM) VPWM = 2V
-90
-70
-50
μA
Oscillation frequency
f(PWM)
C = 150pF
180
225
270
kHz
Amplitude
V(PWM)
1.5
1.7
1.9
Vp-p
Recommended operation frequency
range
fOPR
15
300
kHz
CSD Oscillation Circuit
High level output voltage
VOH(CSD)
2.7
3.0
3.3
V
Low level output voltage
VOL(CSD)
0.8
1.0
1.2
V
Amplitude
V(CSD)
1.75
2.0
2.25
Vp-p
External capacitor charge current
ICHG1(CSD) VCHG1 = 2.0V
-14
-10
-6
μA
External Capacitor Discharge Current
ICHG2(CSD) VCHG2 = 2.0V
8
11
14
μA
Oscillation frequency
f(CSD)
C = 0.068
μF,Design target value *
30
40
50
Hz
Phase comparing output
Output ON resistance (high level)
VPDH
IOH = -100μA
500
700
Ω
Output ON resistance (low level)
VPDL
IOL = 100μA
500
700
Ω
Phase Lock Detection Output
Output ON resistance
VOL(LD)
ILD = 10mA
20
30
Ω
Output leakage current
IL(LD)
VO = 5V
10
μA
Error Amplifier Block
Input offset voltage
VIO(ER)
Design target value *
-10
+10
mV
Input bias current
IB(ER)
-1
+1
μA
High level output voltage
VOH(ER)
IOH = -100μA
EI+0.7
EI+0.85
EI+1.0
V
Low level output voltage
VOL(ER)
IOL = 100μA
EI-1.75
EI-1.6
EI-1.45
V
DC bias level
VB(ER)
-5%
VREG/2
5%
V
Current Control Circuit
Drive gain
GDF
While phase locked
0.5
0.55
0.6
times
Current Limiter Circuit (pins RF and RFS)
Limiter voltage
VRF
0.465
0.515
0.565
V
Under-voltage Protection
Operation voltage
VSD
8.3
8.7
9.1
V
Hyteresis
ΔVSD
0.2
0.35
0.5
V
CLD Circuit
External capacitor charge current
ICLD
VCLD = 0V
-4.5
-3.0
-1.5
μA
Operation voltage
VH(CLD)
3.25
3.5
3.75
V
Thermal Shutdown Operation
Thermal shutdown operation
temperature
TSD
Design target value (Junction temperature)
150
175
°C.
Hysteresis
ΔTSD
Design target value (Junction temperature)
30
°C
CLK pin
External input frequency
fI(CLK)
0.1
10
kHz
High level input voltage
VIH(CLK)
2.0
VREG
V
Low level input voltage
VIL(CLK)
0
1.0
V
Input open voltage
VIO(CLK)
VREG-0.5
VREG
V
Hysteresis
VIS(CLK)
0.2
0.3
0.4
V
High level input current
IIH(CLK)
VCLK = VREG
-10
0
+10
μA
Low level input current
IIL(CLK)
VCLK = 0V
-110
-85
-60
μA
* Design target value, Do not measurement.
Continued on next page.
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