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參數(shù)資料
| 型號： | LV8112V |
| 元件分類： | 運動控制電子 |
| 英文描述： | BRUSHLESS DC MOTOR CONTROLLER, 3 A, PDSO44 |
| 封裝： | 0.275 INCH, SSOP-44 |
| 文件頁數(shù)： | 4/13頁 |
| 文件大?。?/td> | 299K |
| 代理商： | LV8112V |
LV8112V
No.A1645-12/13
6. PWM Frequency
The PWM frequency is determined by using a capacitor C (F) connected to the PWM pin.
fPWM ≈ 1 / (29500 × C ) … 150pF or more
fPWM ≈ 1 / (32000 × C ) … 100pF or more, less than 150pF
The frequency is oscillated at about 225kHz when a capacitor of 150pF is connected.
The GND of a capacitor must be placed as close to the control block GND (GND pin ) of the IC as possible to reduce
influence of the output.
7. Hall Effect Sensor Input Signals
The signal input of the amplitude of hysteresis of 42mV max or more is required in the Hall effect sensor inputs.
Also, an input amplitude of over 100mVp-p is desirable in the Hall effect sensor inputs in view of influence of noise.
If the output waveform (when the phase changes ) is distorted by noise, that noise must be excluded by inputting
capacitors across the inputs.
8. FG Signals
The Hall signal of IN1 is used as the FG signal in the IC. If noise is a problem, the noise of the FG signal can be
excluded by inserting a capacitor between the FGFIL pin and GND.
Note that normal operation becomes impossible if the value of the capacitor is overlarge. Also, note that the trouble of
noise occurs easily when the position of GND of a capacitor is incorrect.
9. Constraint Protection Circuit
This IC has an on-chip constraint protection circuit to protect the IC and the motor in motor constraint mode. when the
CSDSEL pin is set to the high level or open input, if the LD output remains high (unlocked statement) for a fixed
period in the start state, this circuit operates. In the low level setting case, if the FG signal is not switched for a fixed
period in the start state, this circuit is operates. Also, the upper-side output transistor is turned off while the constraint
protection circuit is operating. This time is set by the capacitance of the capacitor attached to the CSD pin.
The set time (in seconds) is 102
× C (μF)
When a capacitor of 0.068
μF is attached, the protection time becomes about 7.0 seconds.
The set time must be set well in advance for the motor start-up time. When the motor is decelerated by switching the
clock frequency, this protection circuit is not operated. To clear the motor constrained state, the S/S pin is switched
into a stop state or the power must be turned off and reapplied. Since the CSD pin also functions as the power-on reset
pin, if the CSD pin were connected directly to ground, the logic circuit goes to the reset state and the speed cannot be
controlled.
Therefore, if the motor constraint protection circuit is not used, a resistor of about 220k
Ω and a capacitor of about
4700pF must be connected in parallel between the CSD pin and GND.
10. Phase Lock Signals
(1) Phase lock range
This IC has no the speed system counter. The speed error range in the phase lock state is indeterminable only by the
characteristics of the IC. ( because the accelerations of the change in FG frequency influences.)
When it is necessary to specify for the speed error as a motor, the value obtained while the motor is actually operating
must be measured. Since the speed error occurs easily when the accelerations of FG is large, the speed error will be
the largest when the IC goes into the lock state during start-up or the unlocked state by switching the clock.
(2) Phase lock signal mask functions
When the IC goes into the lock state during start-up or the unlocked state by switching the clock, the low signal for a
short-time by using the hunting when the IC goes into the locked state is masked. Therefore, the lock signal is output
in stable state. But, the mask time duration causes the delay of the lock signal output. The mask time is set by the
capacitance of the capacitor attached between the CLD pin and GND.
The mask time (seconds) is 1.8
× C (μF)
When a capacitor of 0.1
μF is attached, the mask time becomes about 180ms.
If the signals should be masked completely, the mask time must be set well in advance.
When there is no need for masking, the CLD pin must be left open.
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