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參數(shù)資料
| 型號： | LV573 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 英文描述： | OCTAL D-TYPE TRANSPARENT LATCH (3-State) |
| 中文描述： | 八路D型透明鎖存器（3態(tài)） |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 43K |
| 代理商： | LV573 |
SL74LV573
S ystem Logic
Semiconductor
SLS
AC CHARACTERISICS
(C
L
=50 pF, R
L
=1 K
, t
LH
= t
HL
= 2.5 ns)
Sym
Conditions
Limits
bol
Parameter
Vcc
-40 to +25
°
C
+85
°
C
+125
°
C
Unit
Min
Max
Min
Max Min Max
t
PHL/PLH
Propagation
delay Dn to
Qn
1.2
2.0
2.7
3.0
4.5
V
I
= Vcc or
GND
-
-
-
-
-
150
30
23
18
15
-
-
-
-
-
160
39
29
23
19
-
-
-
-
-
170
49
36
29
24
ns
t
PHL/PLH
Propagation
delay LE to
Qn
1.2
2.0
2.7
3.0
4.5
V
I
= Vcc or
GND
-
-
-
-
-
160
34
28
20
17
-
-
-
-
-
180
43
31
25
21
-
-
-
-
-
190
53
34
31
26
ns
t
PZH/PZL
3-state
output enable
time OE to
Qn
1.2
2.0
2.7
3.0
4.5
V
I
= Vcc or
GND
-
-
-
-
-
140
28
22
17
14
-
-
-
-
-
160
37
28
22
18
-
-
-
-
-
170
48
35
28
23
ns
t
PHZ/PLZ
3-state
outpiut
disable time
OE to Qn
1.2
2.0
2.7
3.0
4.5
V
I
= Vcc or
GND
-
-
-
-
-
160
31
23
20
17
-
-
-
-
-
160
39
29
24
20
-
-
-
-
-
170
48
36
29
24
ns
t
W
LE pulse
width HIGH
1.2
2.0
2.7
3.0
4.5
100
29
21
17
15
-
-
-
-
-
125
34
25
20
18
-
-
-
-
-
150
41
30
24
21
-
-
-
-
-
ns
t
su
Setup time
Dn to LE
1.2
2.0
2.7
3.0
4.5
50
15
11
8
6
-
-
-
-
-
75
17
13
10
8
-
-
-
-
-
100
20
15
12
10
-
-
-
-
-
ns
t
h
Hold time Dn
to LE
1.2
2.0
2.7
3.0
4.5
40
8
8
8
8
-
-
-
-
-
40
8
8
8
8
-
-
-
-
-
40
8
8
8
8
-
-
-
-
-
ns
C
I
Input
capacitance
5.0
ò=+25
7.0
-
ns
C
PD
Power
dissipation
capacitance
per package
5.5
ò=+25
V
I
= Vcc or
GND
52
-
ns
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