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參數(shù)資料
| 型號(hào)： | LV24010LP |
| 元件分類： | 調(diào)諧器 |
| 英文描述： | 1-BAND, AUDIO TUNER, QCC40 |
| 封裝： | 5 X 5 MM, VQLP-40 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 445K |
| 代理商： | LV24010LP |
LV24010LP
No.A0466-14/18
Block 2, Register 0Ah - AUDIO_CTRL2 - Audio Control 2 Register (Write-only)
7
6
5
4
3
2
1
0
Reserved
DEEMP
Reserved
bit 7-6:
Reserved:
should be written with 11b.
bit 5:
DEEMP:
De-emphasis bit.
0 = De-emphasis 50
s.
1 = De-emphasis 75
s.
bit 4-0:
Reserved:
should be written with 00000b.
Block 2, Register 0Bh - PW_SCTRL - Power and Soft Control Register (Write-only)
7
6
5
4
3
2
1
0
SS_CTRL
SM_CTRL
Reserved
PW_RAD
bit 7-5:
SS_CTRL:
Soft stereo control bits (8 levels).
000b = Minimal soft stereo (off).
111b = Maximal soft stereo level.
bit 4-2:
SM_CTRL:
Soft audio mute bits (8 levels).
000b = Minimal audio mute (off).
111b = Maximal soft audio mute level.
bit 1:
Reserved:
should be written with 0.
bit 0:
PW_RAD:
Radio circuitry power bit.
0 = Radio circuitry is switched OFF.
1 = Switch radio circuitry ON.
Note:
PW_RAD is 0 at power up.
Block 4, Register 03h - RDS_FLTDAC - RDS Filter DAC Register (Write-only)
7
6
5
4
3
2
1
0
RFLTDAC[7:0]
bit 7-0:
RFLTDAC[7:0]:
DAC value for RDS filter.
Note:
This register should be programmed with 95% of the value of RDS_OSC register.
Block 4, Register 04h - RDAT_L - RDS Data Low Register (Read-only)
7
6
5
4
3
2
1
0
RD_L[7:0]
bit 7-0:
RD_L[7:0]:
Low byte of the RDS data.
Note:
bit 0 contains the first received bit.
Block 4, Register 05h - RDAT_H - RDS Data High Register (Read-only)
7
6
5
4
3
2
1
0
RD_L[7:0]
bit 7-0:
RD_H[7:0]:
High byte of the RDS data.
Note:
bit 0 contains the first received bit.
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