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參數(shù)資料
| 型號： | LV24010LP |
| 元件分類： | 調(diào)諧器 |
| 英文描述： | 1-BAND, AUDIO TUNER, QCC40 |
| 封裝： | 5 X 5 MM, VQLP-40 |
| 文件頁數(shù)： | 18/18頁 |
| 文件大?。?/td> | 445K |
| 代理商： | LV24010LP |
LV24010LP
No.A0466-9/18
Block 1, Register 04h - SD_OSC - Stereo Decoder Oscillator Register (Write-only)
7
6
5
4
3
2
1
0
SDOSC[7:0]
bit 7-0:
SDOSC[7:0]:
DAC value to control the stereo decoder oscillator.
Note:
Positive DAC control (i.e. the frequency increases with the register’s value)
Block 1, Register 05h - IF_OSC - IF Oscillator Register (Write-only)
7
6
5
4
3
2
1
0
IFOSC[7:0]
bit 7-0:
IFOSC[7:0]:
DAC value to control the IF oscillator.
Note:
Positive DAC control (i.e. the frequency increases with the register’s value).
Block 1, Register 06h - CNT_CTRL - Counters Control Register (Write-only)
7
6
5
4
3
2
1
0
CNT1_CLR
CTAB2
CTAB1
CTAB0
SWP_CNT_L
CNT_EN
CNT_SEL
CNT_SET
bit 7:
CNT1_CLR:
Clear counter 1 bit.
0 = Normal mode.
1 = Clear and keep counter 1 in reset mode.
bit 6-4:
CTAB[2:0]:
Tab select for counter 2 measuring interval bits.
Value
Dec.
Stop value
000b
0
Stop after 2 counts.
001b
1
Stop after 8 counts .
010b
2
Stop after 32 counts.
011b
3
Stop after 128 counts.
100b
4
Stop after 512 counts.
101b
5
Stop after 2048 counts.
110b
6
Stop after 8192 counts.
111b
7
Stop after 32768 counts.
bit 3:
SWP_CNT_L:
Swap counter 1 and counter 2 bit (Active low).
0 = Clock source 1 to counter 2, clock source 2 to counter 1 (swapping)
1 = Clock source 1 to counter 1, clock source 2 to counter 2 (no swap)
bit 2:
CNT_EN:
Enable the currently selected counter bit.
0 = Disable counter (stop counting).
1 = Enable counter (counting mode).
bit 1:
CNT_SEL:
counter select bit.
0 = Select counter 1 for measurement.
1 = Select counter 2 for measurement.
bit 0:
CNT_SET:
Set counters bit.
0 = Normal mode.
1 = Set both counter 1 and counter 2 to FFFFh and keep them set.
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