參數(shù)資料
型號: LTCEMSE-1#PBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: SWITCHING CONTROLLER, PDSO16
封裝: 0.150 INCH, LEAD FREE, PLASTIC, MSOP-16
文件頁數(shù): 11/28頁
文件大?。?/td> 337K
代理商: LTCEMSE-1#PBF
LTC3851-1
19
38511f
APPLICATIONS INFORMATION
Fault Conditions: Current Limit and Current Foldback
The LTC3851-1 includes current foldback to help limit
load current when the output is shorted to ground. If the
output falls below 40% of its nominal output level, the
maximum sense voltage is progressively lowered from
its maximum programmed value to about 25% of the that
value. Foldback current limiting is disabled during soft-
start or tracking. Under short-circuit conditions with very
low duty cycles, the LTC3851-1 will begin cycle skipping
in order to limit the short-circuit current. In this situation
the bottom MOSFET will be dissipating most of the power
but less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time tON(MIN)
of the LTC3851-1 (≈90ns), the input voltage and inductor
value:
ΔIt
V
L
LSC
ON MIN
IN
()
(
)
=
The resulting short-circuit current is:
I
MaxV
R
I
SC
SENSE
LSC
=
14
1
2
/
()
Δ
Programming Switching Frequency
To set the switching frequency of the LTC3851-1, connect
a resistor, RFREQ, between FREQ/PLLFLTR and GND. The
relationship between the oscillator frequency and RFREQ
is shown in Figure 7. A 0.1μF bypass capacitor should be
connected in parallel with RFREQ.
Phase-Locked Loop and Frequency Synchronization
The LTC3851-1 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the top MOSFET
to be locked to the rising edge of an external clock signal
applied to the MODE/PLLIN pin. This phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the external lter
network connected to the FREQ/PLLFLTR pin. Note that the
LTC3851-1 can only be synchronized to an external clock
whose frequency is within range of the LTC3851-1’s internal
VCO.This is guaranteed to be between 250kHz and 750kHz.
A simplied block diagram is shown in Figure 8.
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC , then current is sunk con-
tinuously from the phase detector output, pulling down the
FREQ/PLLFLTR pin. When the external clock frequency is
less than fOSC , current is sourced continuously, pulling up
the FREQ/PLLFLTR pin. If the external and internal frequen-
cies are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to the
phase difference. The voltage on the FREQ/PLLFLTR pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the lter capacitor CLP holds the voltage.
Figure 7. Relationship Between Oscillator Frequency
and Resistor Connected Between FREQ/PLLFLTR and GND
Figure 8. Phase-Locked Loop Block Diagram
RFREQ (kΩ)
20
250
OSCILLATOR
FREQUENCY
(kHz)
300
400
450
500
750
600
60
100
120
38511 F07
350
650
700
550
40
80
140
160
DIGITAL
PHASE/
FREQUENCY
DETECTOR
VCO
2.7V
RLP
CLP
38511 F08
FREQ/PLLFLTR
EXTERNAL
OSCILLATOR
MODE/
PLLIN
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