pin FuncTions (DCB/S6) V+
參數(shù)資料
型號(hào)： LTC6994MPS6-2#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 26/26頁(yè)
文件大?。?/td> 0K
描述： IC DELAY LINE SOT-23-6
特色產(chǎn)品： TimerBlox?
標(biāo)準(zhǔn)包裝： 2,500
系列： TimerBlox®
功能： 可編程
可用的總延遲： 1µs ~ 33.6s
獨(dú)立延遲數(shù)： 1
電源電壓： 2.25 V ~ 5.5 V
工作溫度： -55°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： SOT-23-6 細(xì)型，TSOT-23-6
供應(yīng)商設(shè)備封裝： TSOT-23-6
包裝： 帶卷 (TR)
配用： DC1562A-E-ND - BOARD EVAL LTC6992-3
LTC6994-1/LTC6994-2
9
699412fb
pin FuncTions (DCB/S6)
V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This sup-
ply should be kept free from noise and ripple. It should be
bypassed directly to the GND pin with a 0.1F capacitor.
DIV (Pin 2/Pin 4): Programmable Divider and Polarity
Input. The DIV pin voltage (VDIV) is internally converted
into a 4-bit result (DIVCODE). VDIV may be generated by
a resistor divider between V+ and GND. Use 1% resistors
to ensure an accurate result. The DIV pin and resistors
should be shielded from the OUT pin or any other traces
that have fast edges. Limit the capacitance on the DIV pin
to less than 100pF so that VDIV settles quickly. The MSB
of DIVCODE (POL) selects the delay functionality. For the
LTC6994-1, POL = 0 will delay the rising transition and
POL = 1 will delay the falling transition. For the LTC6994-
2, both transitions are delayed so POL = 1 can be used
to invert the output.
SET (Pin 3/Pin 3): Delay Setting Input. The voltage on the
SET pin (VSET) is regulated to 1V above GND. The amount
of current sourced from the SET pin (ISET) programs the
master oscillator frequency. The ISET current range is
1.25A to 20A. The delayed output transition will be not
occur if ISET drops below approximately 500nA. Once ISET
increases above 500nA the delayed edge will transition.
A resistor connected between SET and GND is the most
accurate way to set the delay. For best performance, use
a precision metal or thin film resistor of 0.5% or better
tolerance and 50ppm/°C or better temperature coefficient.
For lower accuracy applications an inexpensive 1% thick
film resistor may be used.
Limit the capacitance on the SET pin to less than 10pF
to minimize jitter and ensure stability. Capacitance less
than 100pF maintains the stability of the feedback circuit
regulating the VSET voltage.
IN(Pin4/Pin1):LogicInput.Dependingontheversionand
POL bit setting, rising or falling edges on IN will propagate
to OUT after a programmable delay. The LTC6994-1 will
delay only the rising or falling edge. The LTC6994-2 will
delay both edges.
GND (Pin 5/Pin 2): Ground. Tie to a low inductance ground
plane for best performance.
OUT (Pin 6/Pin 6): Output. The OUT pin swings from
GND to V+ with an output resistance of approximately
30Ω. When driving an LED or other low impedance load
a series output resistor should be used to limit source/
sink current to 20mA.
699412 PF
LTC6994
IN
GND
SET
OUT
V+
DIV
C1
0.1F
RSET
R2
R1
V+
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