VSET Drift vs ISET
參數(shù)資料
型號: LTC6994MPS6-2#TRPBF
廠商: Linear Technology
文件頁數(shù): 23/26頁
文件大?。?/td> 0K
描述: IC DELAY LINE SOT-23-6
特色產(chǎn)品: TimerBlox?
標準包裝: 2,500
系列: TimerBlox®
功能: 可編程
可用的總延遲: 1µs ~ 33.6s
獨立延遲數(shù): 1
電源電壓: 2.25 V ~ 5.5 V
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-6 細型,TSOT-23-6
供應(yīng)商設(shè)備封裝: TSOT-23-6
包裝: 帶卷 (TR)
配用: DC1562A-E-ND - BOARD EVAL LTC6992-3
LTC6994-1/LTC6994-2
6
699412fb
VSET Drift vs ISET
VSET Drift vs Supply Voltage
VSET vs Temperature
Typical perForMance characTerisTics
V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.
Delay Error vs RSET (NDIV = 1)
Delay Error vs RSET (NDIV =1)
Delay Error vs DIVCODE
ISET (A)
0
–1.0
0
0.4
0.2
0.6
0.8
1.0
10
15
20
–0.4
–0.2
–0.6
–0.8
5
699412 G16
V SET
(mV)
REFERENCED TO ISET = 10A
SUPPLY (V)
2
–1.0
0
0.4
0.2
0.6
0.8
1.0
4
5
6
–0.4
–0.2
–0.6
–0.8
3
699412 G17
DRIFT
(mV)
REFERENCED TO V+ = 4V
TEMPERATURE (°C)
–50
0.980
1.000
1.010
1.005
1.015
1.020
0
25
50
100 125
0.995
0.990
0.985
–25
75
699412 G18
V SET
(V)
3 PARTS
RSET (k)
50
–5
ERROR
(%)
–3
–1
1
3
100
800
400
200
699412 G10
5
–4
–2
0
2
4
RISING EDGE DELAY
3 PARTS
Delay Error vs RSET
(8 ≤ NDIV ≤ 64)
RSET (k)
50
–5
ERROR
(%)
–3
–1
1
3
100
800
400
200
699412 G11
5
–4
–2
0
2
4
3 PARTS
Delay Error vs RSET (NDIV ≥ 512)
RSET (k)
50
–5
ERROR
(%)
–3
–1
1
3
100
800
400
200
699412 G12
5
–4
–2
0
2
4
3 PARTS
RSET (k)
50
–5
ERROR
(%)
–3
–1
1
3
100
800
400
200
699412 G13
5
–4
–2
0
2
4
FALLING EDGE DELAY
3 PARTS
DIVCODE
0
ERROR
(%)
1
3
2
4
6
8
699412 G14
–1
–3
0
2
4
5
–2
–4
–5
10
12
14
LTC6994-1
RSET = 50k
3 PARTS
RISING EDGE
DELAY
FALLING EDGE
DELAY
Delay Error vs DIVCODE
DIVCODE
0
ERROR
(%)
1
3
2
4
6
8
699412 G15
–1
–3
0
2
4
5
–2
–4
–5
10
12
14
LTC6994-1
RSET = 800k
3 PARTS
RISING EDGE
DELAY
FALLING EDGE
DELAY
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