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| 型號(hào)： | LTC6993HDCB-1#TRMPBF |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 4/26頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MONOSTABLE MULTIVIBRATOR 6DFN |
| 產(chǎn)品培訓(xùn)模塊： | TimerBlox Family Timing Devices |
| 特色產(chǎn)品： | TimerBlox? |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 系列： | LTC®6993 |
| 邏輯類型： | 單穩(wěn)態(tài) |
| 獨(dú)立電路： | 1 |
| 施密特觸發(fā)器輸入： | 無 |
| 傳輸延遲： | 11ns |
| 輸出電流高，低： | 16mA，16mA |
| 電源電壓： | 2.25 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 6-DFN-EP（2x3） |
| 包裝： | 帶卷 (TR) |
| 配用： | DC1562A-D-ND - BOARD EVAL LTC6992-2 |
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LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
12
69931234fb
OPERATION
The LTC6993 is built around a master oscillator with a 1s
minimum period. The oscillator is controlled by the SET
pin current (ISET) and voltage (VSET), with a 1s/50kΩ
conversion factor that is accurate to ±1.7% under typical
conditions.
tMASTER =
1s
50k
VSET
ISET
A feedback loop maintains VSET at 1V ±30mV, leaving
ISET as the primary means of controlling the pulse width.
The simplest way to generate ISET is to connect a resistor
(RSET) between SET and GND, such that ISET = VSET/RSET.
The master oscillator equation reduces to:
tMASTER =1s
RSET
50k
From this equation, it is clear that VSET drift will not affect
the pulse width when using a single program resistor
(RSET). Error sources are limited to RSET tolerance and
the inherent pulse width accuracy
tOUT of the LTC6993.
RSET may range from 50k to 800k (equivalent to ISET
between 1.25A and 20A).
A trigger signal (rising or falling edge on TRIG pin) latches
theoutputtotheactivestate,beginningtheoutputpulse.At
the same time, the master oscillator is enabled to time the
duration of the output pulse. When the desired pulse width
is reached, the master oscillator resets the output latch.
The LTC6993 also includes a programmable frequency
divider which can further divide the frequency by 1, 8, 64,
512, 4096, 215, 218 or 221. This extends the pulse width
duration by those same factors. The divider ratio NDIV is
set by a resistor divider attached to the DIV pin.
tOUT =
NDIV
50k
VSET
ISET
1s
With RSET in place of VSET/ISET the equation reduces to:
tOUT =
NDIV RSET
50k
1s
DIVCODE
TheDIVpinconnectstoaninternal,V+referenced4-bitA/D
converter that determines the DIVCODE value. DIVCODE
programs two settings on the LTC6993:
1. DIVCODE determines the frequency divider setting,
NDIV.
2. DIVCODE determines the polarity of OUT pin, via the
POL bit.
VDIV may be generated by a resistor divider between V+
and GND as shown in Figure 1.
Figure 1. Simple Technique for Setting DIVCODE
69931234 F01
LTC6993
V+
DIV
GND
R1
R2
2.25V TO 5.5V
Table 1 offers recommended 1% resistor values that ac-
curately produce the correct voltage division as well as the
corresponding NDIVandPOLvaluesfortherecommended
resistor pairs. Other values may be used as long as:
1. The VDIV/V+ ratio is accurate to ±1.5% (including resis-
tor tolerances and temperature effects).
2. Thedrivingimpedance(R1||R2)doesnotexceed500kΩ.
If the voltage is generated by other means (i.e., the output
of a DAC) it must track the V+ supply voltage. The last
column in Table 1 shows the ideal ratio of VDIV to the
supply voltage, which can also be calculated as:
VDIV
V+
=
DIVCODE
+ 0.5
16
±1.5%
Forexample,ifthesupplyis3.3VandthedesiredDIVCODE
is 4, VDIV = 0.281 3.3V = 928mV ± 50mV.
Figure 2 illustrates the information in Table 1, showing
that NDIV is symmetric around the DIVCODE midpoint.
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