參數(shù)資料
型號: SY89202UMG
廠商: Micrel Inc
文件頁數(shù): 1/6頁
文件大小: 0K
描述: IC CLK BUFF DVDR MUX 1:8 32-MLF
標準包裝: 60
系列: Precision Edge®
類型: 扇出緩沖器(分配),除法器,多路復用器
電路數(shù): 1
比率 - 輸入:輸出: 1:8
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,PECL
輸出: LVPECL
頻率 - 最大: 1.5GHz
電源電壓: 2.375 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,32-MLF?
供應商設備封裝: 32-MLF?(5x5)
包裝: 管件
產(chǎn)品目錄頁面: 1083 (CN2011-ZH PDF)
其它名稱: 576-1537-5
SY89202UMG-ND
SY89202U
Precision 1:8 LVPECL Fanout Buffer with
Three ÷1/÷2/÷4 Clock Divider Output Banks
Precision Edge is a registered trademark of Micrel, Inc
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (
408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
August 2007
M9999-083107-C
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY89202U is a precision, high-speed, integrated clock
divider LVPECL fanout buffer capable of handling clocks
up to 1.5GHz. Optimized for communications applications,
the three independently controlled output banks are phase
matched and can be configured for pass-through (÷1), ÷2
or ÷4 divide ratios.
The differential input includes Micrel’s unique, 3-pin input
termination architecture that allows the user to interface to
any AC- or DC-coupled signal as small as 100mV
(200mVpp) without any level shifting or termination resistor
networks in the signal path. The low skew, low jitter
outputs are 800mV, 100k compatible LVPECL, with
extremely fast rise/fall times guaranteed to be less than
220ps.
The EN (enable) input guarantees that the ÷1, ÷2 and ÷4
outputs will start from the same state without any runt
pulse after an asynchronous MR (master reset) is
asserted. This is accomplished by enabling the outputs
after
a
four-clock
delay
to
allow
the
counters
to
synchronize.
The SY89202U is part of Micrel’s Precision Edge
product
family.
Datasheets and support documentation can be found on
Micrel’s web site at www.micrel.com.
Precision Edge
Features
Three low-skew LVPECL output banks with
programmable ÷1, ÷2 and ÷4 divider options
Three independently programmable output banks
Guaranteed AC performance over temp and voltage:
– >1.5GHz clock frequency (fMAX)
– <930ps In-to-Out tpd
– <220ps tr/tf
Ultra-low jitter design:
– <1psRMS random jitter (RJ)
– <10psPP total jitter (clock)
Internal input termination
Patent-pending input termination and VT pin accepts
AC- and DC-coupled inputs (CML, PECL, LVDS)
800mV LVPECL output swing
CMOS/TTL-compatible output enable (EN) and divider
select control
Power supply 2.5V +5% or 3.3V +10%
–40oC to +85oC industrial temperature range
Available in 32-pin QFN package
Applications
All SONET/SDH channel select applications
All Fibre Channel multi-channel select applications
All Gigabit Ethernet multi-channel select applications
Markets
LAN/WAN
Enterprise servers
ATE
Test and measurement
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