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參數(shù)資料
| 型號(hào)： | LTC694-3.3 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 3.3V Microprocessor Supervisory Circuits(3.3VμP監(jiān)控電路) |
| 中文描述： | 3.3微處理器監(jiān)控電路（3.3VμP監(jiān)控電路） |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 143K |
| 代理商： | LTC694-3.3 |
11
LTC 694-3.3/LTC 695-3.3
U
S
A
O
PPLICATI
U
U
3.3V
2.4V
0.1
μ
F
10
μ
F
V
BATT
V
CC
LTC695-3.3
V
OUT
GND
694/5-3.3 F06
V
CC
RESET
CE IN
RESET
CE OUT
0.1
μ
F
TO
μ
P
FROM DECODER
CS
30ns PROPAGATION DELAY
62512
RAM
GND
+
Figure 9. Monitoring RegulatedDC Supply with the
LTC694-3.3/LTC695-3.3’s Power-Fail Comparator
10
μ
F
694/5-3.3 F09
0.1
μ
F
TO
μ
P
V
IN
≥
6.5V
+
10
μ
F
+
R3
2.7M
3.3V
R1
27k
R2
16k
R5
5k
V
CC
GND
PFO
PFI
LTC694-3.3
LTC695-3.3
R4
10k
V
IN
OUT SENSE
V
OUT
LT1129-3.3
SHDN
ADJ
Figure 6. A Typical Nonvolatile CMOS RAM Application
Figure 7. Write Protect for RAM with LTC694-3.3
3.3V
2.4V
0.1
μ
F
10
μ
F
V
BATT
V
CC
V
OUT
GND
694/5-3.3 F07
V
CC
RESET
0.1
μ
F
CS
62128
RAM
CS1
CS2
GND
LTC694-3.3
+
100
μ
F
694/5-3.3 F08
V
CC
0.1
μ
F
R4
10k
10
μ
F
TO
μ
P
PFO
PFI
GND
V
IN
≥
5V
LTC694-3.3
LTC695-3.3
R1
51k
R2
16k
R3
200k
3.3V
V
IN
OUT SENSE
V
OUT
LT1129-3.3
SHDN
ADJ
+
+
Figure 8. Monitoring UnregulatedDC Supply with the
LTC694-3.3/LTC695-3.3’s Power-Fail Comparator
comparing the power failure input (PFI) with an internal
1.3V reference.
PFO goes low when the voltage at the PFI pin is less than
1.3V. Typically PFI is driven by an external voltage divider
(R1 and R2 in Figures 8 and 9) which senses either an
unregulated DC input or a regulated 3.3V output. The
voltage divider ratio can be chosen such that the voltage
at the PFI pin falls below 1.3V several milliseconds before
the 3.3V supply falls below the maximum reset voltage
threshold 3.0V. PFO is normally used to interrupt the
microprocessor to execute shutdown procedure between
PFO and RESET or RESET.
The power-fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resis-
tor between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip
points in the comparator are established as follows:
When PFO output is low, R3 sinks current from the
summing junction at the PFI pin.
V =1.3V 1+R1
R2
R1
R3
+
When PFO output is high, the series combination of R3 and
R4 source current into the PFI summing junction.
V
1.3V 1
R2±(3.3V ±1.3V)R1
1.3V(R3 R4)
L
=
+
Assuming R4
R3,V
3 VR1
=
.3
R3
HYSTERESIS
<<
Example 1:
The circuit in Figure 8 demonstrates the use of
the power-fail comparator to monitor the unregulated
power supply input. Assuming the the rate of decay of the
supply input V
IN
is 100mV/ms and the total time to execute
a shutdown procedure is 8ms. Also the noise of V
IN
is
200mV. With these assumptions in mind, we can reason-
ably set V
L
= 5V which is 1.6V greater than the sum of
maximum reset voltage threshold and the dropout voltage
of the LT1129-3.3 (3V + 0.4V) and V
HYSTERESIS
= 850mV.
相關(guān)PDF資料 |
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| LTC695 | Microprocessor Supervisory Circuits |
| LTC695-3.3 | 3.3V Microprocessor Supervisory Circuits |
| LTC695C | Microprocessor Supervisory Circuits |
| LTC695CN | Microprocessor Supervisory Circuits |
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