參數(shù)資料
型號(hào): LTC694-3.3
廠商: Linear Technology Corporation
英文描述: 3.3V Microprocessor Supervisory Circuits(3.3VμP監(jiān)控電路)
中文描述: 3.3微處理器監(jiān)控電路(3.3VμP監(jiān)控電路)
文件頁(yè)數(shù): 10/16頁(yè)
文件大?。?/td> 143K
代理商: LTC694-3.3
10
LTC 694-3.3/LTC 695-3.3
Table 1 shows the state of each pin during battery back-up.
When the battery switchover section is not used, connect
V
BATT
to GND and V
OUT
to V
CC
.
Memory Protection
The LTC695-3.3 includes memory protection circuitry
which ensures the integrity of the data in memory by
preventing write operations when V
CC
is at invalid level.
Two additional pins, CE IN and CE OUT, control the Chip
Enable or Write inputs of CMOS RAM. When V
CC
is 3.3V,
CE OUT follows CE IN with a typical propagation delay of
30ns. When V
CC
falls below the reset voltage threshold or
V
BATT
, CE OUT is forced high, independent of CE IN. CE
OUT is an alternative signal to drive the CE, CS, or Write
input of battery backed up CMOS RAM. CE OUT can also
be used to drive the Store or Write input of an EEPROM,
EAROM or NOVRAM to achieve similar protection. Figure
5 shows the timing diagram of CE IN and CE OUT.
CE IN can be derived from the microprocessor’s address
decoder output. Figure 6 shows a typical nonvolatile
CMOS RAM application.
Memory protection can also be achieved with the LTC694-
3.3 by using RESET as shown in Figure 7.
Power-Fail Warning
The LTC694-3.3/LTC695-3.3 generate a Power Failure
Output (PFO) for early warning of failure in the
microprocessor’s power supply. This is accomplished by
Figure 5. Timing Diagram for CE IN and CE OUT
U
S
A
O
PPLICATI
W
U
I FOR ATIO
U
2.7M
0.1
μ
F
V
BATT
LTC694-3.3
LTC695-3.3
GND
694/5-3.3 F04
10
Figure 4. 10
/0.1
μ
F Combination Eliminates Inductive
Overshoot and Prevents Spurious Resets During Battery
Replacement. The 2.7M Pulls the V
BATT
Pin to Ground
While the Battery is Removed, Eliminating Spurious Resets
SIGNAL
V
CC
V
OUT
V
BATT
BATT ON
PFI
PFO
RESET
RESET
LOW LINE Logic low
WDI
WDO
CE IN
CE OUT
OSC IN
OSC SEL
STATUS
C2 monitors V
CC
for active switchover
V
OUT
is connected to V
BATT
through an internal PMOS switch
The supply current is 1
μ
A maximum.
Logic high. The open-circuit output voltage is equal to V
OUT
Power failure input is ignored
Logic low
Logic low
Logic high. The open-circuit output voltage is equal to V
OUT
Watchdog input is ignored.
Logic high. The open-circuit output voltage is equal to V
OUT
Chip Enable input is ignored.
Logic high. The open-circuit output voltage is equal to V
OUT
OSC IN is ignored
OSC SEL is ignored
Table 1. Input and Output Status in Battery Back-Up Mode
V
CC
V1
CE IN
V
OUT
= V
BATT
CE OUT
V
OUT
= V
BATT
V2
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
694/5-3.3 F05
相關(guān)PDF資料
PDF描述
LTC695CSW-3.3 3.3V Microprocessor Supervisory Circuits
LTC695 Microprocessor Supervisory Circuits
LTC695-3.3 3.3V Microprocessor Supervisory Circuits
LTC695C Microprocessor Supervisory Circuits
LTC695CN Microprocessor Supervisory Circuits
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