參數(shù)資料
型號(hào)： LTC6912HGN-1#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 8/24頁(yè)
文件大小： 0K
描述： IC PGA DIGITAL R-R DUAL 16SSOP
標(biāo)準(zhǔn)包裝： 2,500
放大器類型： 可編程增益
電路數(shù)： 2
輸出類型： 滿擺幅
轉(zhuǎn)換速率： 26 V/µs
增益帶寬積： 33MHz
電壓 - 輸入偏移： 125µV
電流 - 電源： 2.25mA
電流 - 輸出 / 通道： 35mA
電壓 - 電源，單路/雙路(±)： 2.7 V ~ 10.5 V，±2.7 V ~ 5.25 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 帶卷 (TR)
LTC6912
16
6912fa
INA, INB: Analog Inputs. The input signal to the A channel
amplifier of the LTC6912-X is the voltage difference be-
tween the INA pin and AGND pin. Likewise, the input signal
to the B channel amplifier of the LTC6912-X is the voltage
difference between the INB pin and AGND pin. The INA (or
INB) pin connects internally to a digitally controlled resis-
tance whose other end is a current summing point at the
same potential as the AGND pin (Figure 1). At unity gain,
the value of this input resistance is approximately 10k
and the INA (or INB) pin voltage range is rail-to-rail (V+ to
V–). At gain settings above unity, the input resistance falls.
The linear input range at INA and INB also falls inversely
proportional to the programmed gain. Tables 1 and 2
summarize this behavior. The higher gains are designed to
boost lower level signals with good noise performance. In
the “zero” gain state (state = 0), or in software shutdown
(state = 8) analog switches disconnect the INA or INB pin
internally and this pin presents a very high input resis-
tance. In the “zero” gain state (state = 0), the input may
vary from rail to rail but the output is insensitive to it and
is forced to the AGND potential. Circuitry driving the INA
and INB pins must consider the LTC6912-X’s input resis-
tance, its process variance, and the variation of this
resistance from gain setting to gain setting. Signal sources
with significant output resistance may introduce a gain
error as the source’s output resistance and the LTC6912-
X’s input resistance forms a voltage divider. This is espe-
cially true at higher gain settings where the input resis-
tance is the lowest.
UU
U
PI FU CTIO S
Figure 1. GN-16 Block Diagram
+
–
+
–
MOS INPUT
OP AMP
MOS INPUT
OP AMP
V+
V–
SHDN
CS/LD
DATA
CLK
6912 BD
LOWER
NIBBLE
UPPER
NIBBLE
8-BIT
LATCH
8-BIT
SHIFT-REGISTER
INPUT R ARRAY
FEEDBACK R ARRAY
INPUT R ARRAY
FEEDBACK R ARRAY
CHANNEL A
CHANNEL B
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
5
3
1
16
15
13
14
12
10
11
6
7
8
9
2
4
NC
INA
AGND
V–
OUT A
OUT B
NC
V+
NC
DGND
DOUT
INB
100k
In single supply voltage applications, the LTC6912-X’s DC
ground reference for both input and output is AGND, not
V–. With increasing gains, the LTC6912-X’s input voltage
range for an unclipped output is no longer rail-to-rail but
diminishes inversely to gain, centered about the AGND
potential.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LTC6912-2 Gain Shift vs
Temperature (Heavy Load)
TEMPERATURE (°C)
–50
25
75
–25
0
50
100
125
GAIN
CHANGE
(dB)
0.25
0
–0.25
–0.50
–0.75
–1.00
6912 G26
VS = 5V
RL = 500
GAIN = 1
GAIN = 8
GAIN = 64
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