參數(shù)資料
型號(hào)： LTC6912HGN-1#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 10/24頁(yè)
文件大?。?/td> 0K
描述： IC PGA DIGITAL R-R DUAL 16SSOP
標(biāo)準(zhǔn)包裝： 2,500
放大器類型： 可編程增益
電路數(shù)： 2
輸出類型： 滿擺幅
轉(zhuǎn)換速率： 26 V/µs
增益帶寬積： 33MHz
電壓 - 輸入偏移： 125µV
電流 - 電源： 2.25mA
電流 - 輸出 / 通道： 35mA
電壓 - 電源，單路/雙路(±)： 2.7 V ~ 10.5 V，±2.7 V ~ 5.25 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 帶卷 (TR)
LTC6912
18
6912fa
SHDN (GN-16 ONLY): CMOS Compatible Logic Hardware
Shutdown Input. The LTC6912-X has two shutdown modes.
One is a software shutdown state which can be software
programmed into either Channel A, Channel B, or both.
The software shutdown, when programmed to a particular
channel (state = 8), will disable that channel’s amplifier
and tri-state open its analog input and analog output. The
serial interface, however is still active. A hardware shut-
down occurs when the SHDN pin is pulled to the positive
rail. In this condition, both amplifiers and serial interface
are disabled. The SHDN pin is allowed to swing from V– to
10.5V above V–, regardless of V+ so long as the logic levels
meet the minimum requirements specified in the Electrical
Characteristics table. The SHDN pin is a high impedance
CMOS logic input, but has a small pull-down current
source (<10
A) which will force SHDN low if the logic
input is externally floated. On initial power up (with SHDN
open), or coming out of the hardware shutdown mode
(pulling SHDN to V–), both amplifiers are reset into the
power-on reset state (software shutdown mode, state = 8)
for both channels.
CS/LD: TTL/CMOS Compatible Logic Input. When this pin
is asserted low, the CLK pin is enabled, and the 8-bit shift
register serially shifts the shift register contents and
whatever data is present on the DIN pin into the shift
register on the rising edge of CLK. On the rising edge of
CS/LD, the contents of the shift register data are loaded
into the eight bit latch which configures the gain state of
both channel A and channel B amplifiers. A logic high on
CS/LD inhibits the CLK signal internally to the IC.
DIN: TTL/CMOS Compatible Logic Serial Data Input. The
serial interface is synchronously loaded MSB first via DIN
on the rising edge of CLK with CS/LD asserted low.
CLK: TTL/CMOS Compatible Logic Input. With CS/LD
asserted low, the clock synchronizes the loading of the
serial shift register on its rising and falling edges. Data is
shifted in at DIN on the rising edge of CLK and is shifted out
on DOUT on the falling edge of CLK.
DOUT: TTL/CMOS Compatible Logic Output. The MSB of
the shift register contents is shifted out at DOUT on the
falling edge of CLK. The output at DOUT swings between V+
and DGND, and is rated to drive approximately 15pF.
DGND: Digital Ground: The DGND pin defines the potential
from which LOGIC levels VIH and VIL for the 3-wire serial
digital interface are referenced. The recommended con-
nection of DGND depends on how power is applied to the
LTC6912 (See Figures 2, 3, and 4). (CAVEAT: Under no
conditions is DGND to exceed either supply pins V+ and
V–, which could result in damage to the IC if not current
limited.)
Single power supply applications typically use V– for the
system signal ground. The preferred connection for DGND
is therefore V– (See Figure 2).
Dual supply applications with symmetrical supplies (such
as
±5V) have a natural system ground potential of zero
volts, in which the DGND pin can be tied to, making the
zero volt ground plane the logic reference (Figure 3).
Finally, if dual asymmetrical power supplies are used, the
system ground is still the natural ground plane voltage.
V–, V+: Power Supply Pins. The V+ and V– pins should be
bypassed with 0.1
F capacitors to an adequate analog
ground plane using the shortest possible wiring. Electri-
cally clean supplies and a low impedance ground are
important for the high dynamic range available from the
LTC6912 (see further details under the AGND pin descrip-
tion). Low noise linear power supplies are recommended.
Switching power supplies require special care to prevent
switching noise coupling into the signal path, reducing
dynamic range.
UU
U
PI FU CTIO S
Figure 4. Asymmetrical Dual Supply Ground Plane Connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC6912-X
SERIAL
INTERFACE
0.1
F
0.1
F
V+
V–
DIGITAL GROUND PLANE
ANALOG GROUND PLANE
≥0.1F
V+ + V–
2
REFERENCE
6912 F04
SINGLE-POINT
SYSTEM GND
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