參數(shù)資料
型號(hào)： LTC4302IMS-1#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 14/20頁(yè)
文件大?。?/td> 298K
描述： IC BUFFER 2-WIRE BUS 10-MSOP
標(biāo)準(zhǔn)包裝： 2,500
類型： 熱交換開關(guān)
應(yīng)用： 通用型緩沖器/總線擴(kuò)展器
內(nèi)部開關(guān)： 是
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 帶卷 (TR)
LTC4302-1/LTC4302-2
14
sn430212 430212fs
OPERATIO
Connection Circuitry
Masters on the SDAIN and SCLIN busses can address the
LTC4302 and command it to connect SDAIN to SDAOUT
and SCLIN to SCLOUT as described in the Write One or
Two Bytes section. Once this connection occurs, masters
on the card are then able to read from and write to the part
via the SDAOUT and SCLOUT pins. However, whenever
the two sides are disconnected, the command to recon-
nect must come from SDAIN and SCLIN.
Once the connection circuitry is activated, the functional-
ity of the SDAIN and SDAOUT pins is identical. A low
forced on either pin at any time results in both pin voltages
being low. Masters must pull the bus voltages below 0.4V
worst-case with respect to the LTC4302s ground pin to
ensure proper operation. SDAIN and SDAOUT enter a logic
high state only when all devices on both SDAIN and
SDAOUT busses force a high. The same is true for SCLIN
and SCLOUT. This important feature ensures that clock
stretching, clock arbitration and the acknowledge protocol
always work, regardless of how the devices in the system
are connected to the LTC4302.
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the backplane
and the card capacitances isolated. Because of this isola-
tion, the waveforms on the backplane busses look slightly
different from the corresponding card bus waveforms.
Input-to-Output Offset Voltage
When a logic low voltage, V
LOW1
 is driven on any of the
LTC4302s data or clock pins, the LTC4302 regulates the
voltage on the other side (V
LOW2
) to a slightly higher
voltage, as directed by the following equation:
V
LOW2
 (typical) = V
LOW1
 + 75mV + (V
BUS
/R) " 70&
where R is the bus pull-up resistance on V
LOW2
 in ohms
and V
BUS
 is the supply voltage to which R is connected.
For example, if a device is forcing SDAOUT to 10mV, and
if V
CC
 = 3.3V and the pull-up resistor R on SDAIN is 10k,
then the voltage on SDAIN = 10mV + 75mV + (3.3V/10k)
" 70& = 108mV (typical). See the Typical Performance
Characteristics section for curves showing the offset
voltage as a function of V
CC
 and R.
Propagation Delays
During a rising edge, the rise time on each side is deter-
mined by the combined pull-up current of the LTC4302
boost current and the bus resistor and the equivalent
capacitance on the line. If the pull-up currents are the
same, a difference in rise time occurs that is directly
proportional to the difference in capacitance between the
two sides. This effect is displayed in Figure 10 for V
CC
 =
3.3V and a 10k pull-up resistor on each side (50pF on one
side and 150pF on the other). Since the output side has
less capacitance than the input, it rises faster and the
effective t
PLH
 is negative.
There is a finite propagation delay, t
PHL
, through the
connection circuitry for falling waveforms. Figure 11 shows
the falling waveforms for the same V
CC
, pull-up resistors
and equivalent capacitance conditions used in Figure 10.
An external N-Channel MOSFET device pulls down the
voltage on the side with 150pF capacitance; the LTC4302
OUTPUT
SIDE
50pF
INPUT
SIDE
150pF
4032 F10
Figure 10. Input-Output Connection t
PLH
INPUT
SIDE
150pF
OUTPUT
SIDE
50pF
4032 F11
Figure 11. Input-Output Connection t
PHL
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