參數(shù)資料
型號: LTC4278CDKD#PBF
廠商: Linear Technology
文件頁數(shù): 30/42頁
文件大?。?/td> 0K
描述: IC PD IEEE 802.3AT 25.5W 32-DFN
產(chǎn)品培訓模塊: Power over Ethernet
標準包裝: 52
控制器類型: 供電設備接口控制器(PD)
接口: IEEE 802.3af
電源電壓: 4.5 V ~ 20 V
電流 - 電源: 6.4mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-WFDFN 裸露焊盤
供應商設備封裝: 32-DFN(7x4)裸露焊盤
包裝: 管件
產(chǎn)品目錄頁面: 1338 (CN2011-ZH PDF)
LTC4278
36
4278fc
APPLICATIONS INFORMATION
Capacitor Selection
In a flyback converter, the input and output current flows
in pulses, placing severe demands on the input and output
filter capacitors. The input and output filter capacitors are
selected based on RMS current ratings and ripple voltage.
Select an input capacitor with a ripple current rating
greater than:
IRMS(PRI) =
PIN
VIN(MIN)
1– DCMAX
DCMAX
Continuing the example:
IRMS(PRI) =
29.5W
41V
1– 49.4%
49.4%
= 0.728A
Keep input capacitor series resistance (ESR) and
inductance (ESL) small, as they affect electromagnetic
interferencesuppression.Insomeinstances,highESRcan
alsoproducestabilityproblemsbecauseflybackconverters
exhibit a negative input resistance characteristic. Refer to
Application Note 19 for more information.
The output capacitor is sized to handle the ripple current
and to ensure acceptable output voltage ripple. The output
capacitor should have an RMS current rating greater than:
IRMS(SEC) =IOUT
DCMAX
1– DCMAX
Continuing the example:
IRMS(SEC) = 5.3A
49.4%
1– 49.4%
= 5.24A
This is calculated for each output in a multiple winding
application.
ESRandESLalongwithbulkcapacitancedirectlyaffectthe
output voltage ripple. The waveforms for a typical flyback
converter are illustrated in Figure 17.
The maximum acceptable ripple voltage (expressed as a
percentage of the output voltage) is used to establish a
starting point for the capacitor values. For the purpose of
simplicity, we will choose 2% for the maximum output
OUTPUT VOLTAGE
RIPPLE WAVEFORM
SECONDARY
CURRENT
PRIMARY
CURRENT
IPRI
VCOUT
4278 F17
RINGING
DUE TO ESL
IPRI
N
VESR
Figure 17. Typical Flyback Converter Waveforms
ripple, divided equally between the ESR step and the
charging/discharging
ΔV. This percentage ripple changes,
depending on the requirements of the application. You can
modify the following equations.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor is determined by:
ESRCOUT ≤1%
VOUT 1–DCMAX
(
)
IOUT
The other 1% is due to the bulk C component, so use:
COUT
IOUT
1% VOUT fOSC
In many applications, the output capacitor is created from
multiple capacitors to achieve desired voltage ripple,
reliability and cost goals. For example, a low ESR ceramic
capacitor can minimize the ESR step, while an electrolytic
capacitor satisfies the required bulk C.
Continuing our example, the output capacitor needs:
ESRCOUT ≤1%
5V 1– 49.4%
(
)
5.3A
= 4m
COUT
5.3A
1% 5 200kHz
= 600F
These electrical characteristics require paralleling several
low ESR capacitors possibly of mixed type.
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