
LTC4269-2
42692fb
elecTrical characTerisTics The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SOUT High Level
IGATE = –25mA, VIN = 12V COMP = 2.5V, FB = 1V
10
V
SOUT Active Pull-Off in Shutdown
VIN = 5V, SD_VSEC = 0V, SOUT = 1V
1
mA
SOUT to OUT (Rise) DELAY (tDELAY)
COMP = 2.5V, FB = 1V (Note 16)
RDELAY = 120k
40
120
ns
VDELAY
0.9
V
OUT Driver
OUT Rise Time
FB = 1V, CL = 1nF (Notes 15, 16)
50
ns
OUT Fall Time
FB = 1V, CL = 1nF (Notes 15, 16)
30
ns
OUT Clamp Voltage
IGATE = 0A, COMP = 2.5V, FB = 1V
11.5
13
14.5
V
OUT Low Level
IGATE = 20mA
IGATE = 200mA
0.45
1.25
0.75
1.8
V
OUT High Level
IGATE = –20mA, VIN = 12V COMP = 2.5V, FB = 1V
IGATE = –200mA, VIN = 12V COMP = 2.5V, FB = 1V
9.9
9.75
V
OUT Active Pull-Off in Shutdown
VIN = 5V, SD_VSEC = 0V, OUT = 1V
20
mA
OUT Max Duty Cycle
COMP = 2.5V, FB = 1V, RDELAY = 10k (fOSC = 200kHz),
VIN = 10V, SD_VSEC = 1.4V, SS_MAXDC = VREF
83
90
%
OUT Max Duty Cycle Clamp
COMP = 2.5V, FB = 1V, RDELAY = 10k (fOSC = 200kHz),
VIN = 10V
SD_VSEC = 1.32V, SS_MAXDC = 1.84V
SD_VSEC = 2.64V, SS_MAXDC = 1.84V
63.5
25
72
33
80.5
41
%
Soft-Start
SS_MAXDC Low Level: VOL
ISS_MAXDC = 150A, OC = 1V
0.2
V
SS_MAXDC Soft-Start Reset Threshold
Measured on SS_MAXDC
0.45
V
SS_MAXDC Active Threshold
FB + 1V, DC > 0%
0.8
V
SS_MAXDC Input Current
(Soft-Start Pull-Down: IDIS)
SS_MAXDC = 1V, SD_VSEC = 1.4V, OC = 1V
800
A
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Pins with 100V absolute maximum guaranteed for T ≥ 0°C,
otherwise 90V.
Note 3: PWRGD voltage clamps at 14V with respect to VNEG.
Note 4: In applications where the VIN pin is supplied via an external RC
network from a system VIN > 25V, an external Zener with clamp voltage
VIN ON(MAX) < VZ < 25V should be connected from the VIN pin to GND.
Note 5: All voltages are with respect to VPORTN pin unless otherwise noted.
Note 6: Input voltage specifications are defined with respect to LTC4269-2
pins and meet IEEE 802.3af/at specifications when the input diode bridge
is included.
Note 7: Signature resistance is measured via the
V/I method with the
minimum
V of 1V. The LTC4269-2 signature resistance accounts for the
additional series resistance in the input diode bridge.
Note 8: An invalid signature after the 1st classification event is mandated
by IEEE 802.3at standard. See the Applications Information section.
Note 9: Class accuracy is respect to the ideal current defined as
1.237/RCLASS and does not include variations in RCLASS resistance.
Note 10: This parameter is assured by design and wafer level testing.
Note 11: Voltages are with respect to GND unless otherwise specified.
Tested with COMP open, VFB = 1.4V, RROSC = 178k, VSYNC = 0V, VSS(MAXDC)
set to VREF (but electrically isolated), CVREF = 0.1F, VSD_VSEC = 2V, RBLANK
= 121k, RDELAY = 121k, VISENSE = 0V, VOC = 0V, COUT = 1nF, VIN = 15V,
SOUT open, unless otherwise specified.
Note 12: Guaranteed by correlation to static test.
Note 13: VIN start-up current is measured at VIN = VIN(ON) – 0.25V and
scaled by
× 1.18 (to correlate to worst-case VIN start-up current at VIN(ON).
Note 14: Maximum recommended SYNC frequency = 500kHz.
Note 15: Guaranteed but not tested.
Note 16: Timing for R = 40k derived from measurement with R = 240k.