參數(shù)資料
型號: LTC4269CDKD-2
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: SWITCHING CONTROLLER, 560 kHz SWITCHING FREQ-MAX, PDSO32
封裝: 7 X 4 MM, PLASTIC, M0-229, DFN-32
文件頁數(shù): 18/34頁
文件大?。?/td> 383K
代理商: LTC4269CDKD-2
LTC4269-2
42692fb
applicaTions inForMaTion
where:
RS = sense resistor in source of primary MOSFET
IRIPPLE = IP-P ripple current in the output inductor L1
NS = number of transformer secondary turns
NP = number of transformer primary turns
Programming Slope Compensation
TheLTC4269-2usesacurrentmodearchitecturetoprovide
fast response to load transients and to ease frequency
compensation requirements. Current mode switching
regulators which operate with duty cycles above 50%
and have continuous inductor current must add slope
compensation to their current sensing loop to prevent
subharmonic oscillations. (For more information on slope
compensation, see Application Note 19.) The LTC4269-2
has programmable slope compensation to allow a wide
range of inductor values, to reduce susceptibility to PCB
generated noise and to optimize loop bandwidth. The
LTC4269-2 programs slope compensation by inserting a
resistor, RSLOPE, in series with the ISENSE pin (Figure 13).
The LTC4269-2 generates a current at the ISENSE pin which
is linear from 0% duty cycle to the maximum duty cycle
of the OUT pin. A simple calculation of ISENSE RSLOPE
gives an added ramp to the voltage at the ISENSE pin for
programmable slope compensation. (See both graphs
ISENSE Pin Current vs Duty Cycle and ISENSE Maximum
Threshold vs Duty Cycle in the Typical Performance
Characteristics section.)
CURRENT SLOPE = 35A DC
V(ISENSE) = VSOURCE + (ISENSE RSLOPE)
ISENSE = 8A + 35DC A
DC = DUTY CYCLE
FOR SYNC OPERATION
ISENSE(SYNC) = 8A + (k 35DC)A
k = fOSC/fSYNC
42692 F13
ISENSE
OUT
LTC4269-2
OC
RS
RSLOPE
VSOURCE
Figure 13. Programming Slope Compensation
42692 F14
DELAY
LTC4269-2
RDELAY
tDELAY
SOUT
OUT
Figure 14. Programming SOUT and OUT Delay: tDELAY
Programming Synchronous Rectifier Timing:
SOUT to OUT delay (‘tDELAY’)
The LTC4269-2 has an additional output SOUT which pro-
vides a
±50mA peak drive clamped to 12V. In applications
requiring synchronous rectification for high efficiency,
the LTC4269-2 SOUT provides a sync signal for second-
ary side control of the synchronous rectifier MOSFETs
(Figure 14). Timing delays through the converter can
cause non-optimum control timing for the synchronous
rectifier MOSFETs. The LTC4269-2 provides a program-
mable delay (tDELAY, Figure 14) between SOUT rising
edge and OUT rising edge to optimize timing control for
the synchronous rectifier MOSFETs to achieve maximum
efficiency gains. A resistor RDELAY connected from the
DELAY pin to GND sets the value of tDELAY. Typical values
for tDELAY range from 10ns with RDELAY = 10k to 160ns
with RDELAY = 160k (see graph in the Typical Performance
Characteristics section).
Programming Maximum Duty Cycle Clamp
For forward converter applications, a maximum switch
duty cycle clamp which adapts to transformer input volt-
age is necessary for reliable control of the MOSFETs. This
volt-second clamp provides a safeguard for transformer
resetthatpreventstransformersaturation.TheLTC4269-2
SD_VSEC and SS_MAXDC pins provide a capacitor-less,
programmable volt-second clamp solution using simple
resistor ratios (Figure 15).
An increase of voltage at the SD_VSEC pin causes the
maximumdutycycleclamptodecrease.DerivingSD_VSEC
from a resistor divider connected to system input voltage
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